Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1999-05-21
2002-11-12
Gaffin, Jeffrey (Department: 2187)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S400000, C713S500000, C710S008000, C710S104000, C712S015000
Reexamination Certificate
active
06480967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of electronic systems, and in particular to systems comprising components having potentially different reset strategies.
2. Description of Related Art
To contain and potentially shorten the design and development cycle time for large scale systems, previously designed components, or modules, are commonly used. Such modules, having been designed for systems having differing requirements, often have differing clock and timing constraints. Some modules, for example, may employ a positive-edge-triggered clocking scheme, others may employ a negative-edge-triggered clocking scheme, while others may be level sensitive, multi-phased, and so on. In like manner, the convention used for resetting each module may differ. Asynchronous or synchronous reset strategies may be employed, and often a combination of both is common. For each module, the reset strategy employed introduces timing constraints relative to the particular clocking scheme employed. Examples of such timing constraints include: a synchronous reset must arrive at the module a specified duration before the active edge of the clock and/or be held at its active state for a specified duration after the clock edge; an asynchronous reset should not be released in close proximity to a change of clock state in a level sensitive clocking design; a reset signal should not be asserted, or de-asserted, in close proximity to an assertion or desertion of a set signal; and so on. From a systems viewpoint, the varying reset and clocking strategies produce a combinatorially complex set of design constraints.
To accommodate the varying clocking strategies among modules, conventional systems include a module-clock-generator that generates the various clocking signals, at appropriate frequency and phase relative to each other for proper system operation. Accommodation of the varying reset strategies is commonly somewhat less structured. Typically, because of the combinatorial nature of the problem, specific reset circuitry is designed for each module, or for each set of modules having a similar combination of reset and clock configurations. While the design of each reset circuit may not be unduly burdensome, the system level design task of properly defining, configuring, and testing each of these circuits can be significant.
The testing task for reset circuits is particularly burdensome because of the difficulties associated with timing related anomalies. In a well structured system design, the system designer strives to use synchronous functions and operations to minimize timing related problems. Because of the lack of standardization for reset strategies, and the variety of alternatives available, including asynchronous operation, the likelihood of a timing related error is high, and the cost of isolating and preventing the particular circumstances that produce the problematic timing sequences is high.
The use of specific, time-dependent, reset circuits also minimizes the likelihood that systems designed with such circuits will “scale” as technologies change, or as other features are added to the system. Similarly, the use of such a system as a future module in a larger system will only serve to exacerbate the problems associated with modules having differing reset strategies and timing constraints.
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to provide a reset architecture that provides for a reliable and robust system reset capability that is independent of the reset configurations used in the modules that comprise the system. It is another object of this invention to provide a reset architecture that is modular. It is another object of this invention to provide a reset architecture that is scalable. It is another object of this invention to provide a reset architecture that is easy to test. It is another object of this invention to provide a reset architecture that reduces the complexity associated with system tests.
These objects, and others, are achieved by providing a reset module that operates in conjunction with the system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. In a preferred embodiment, a reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.
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Gartlan Michael
Jensen Rune Hartung
Biren Steven R.
Gaffin Jeffrey
Koninklijke Philips Electronics , N.V.
Mai Rijue
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