Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1993-07-15
2000-02-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711154, G06F 1314
Patent
active
060214775
ABSTRACT:
A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is coupled to and responsive to a signal asserted on the second bus by one of the memory units selected by the transmitted memory address. The asserted signal indicates an access speed of the selected memory unit, and specifies a duration of the memory access on an access-by-access basis so as to make a duration of the memory access cycle compatible with the access speed of at least the semiconductor memory devices of the selected memory unit.
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Chan Eddie P.
Ellis Kevin L.
Samsung Electronics Co,. Ltd
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