Static information storage and retrieval – Read/write circuit – Serial read/write
Reexamination Certificate
2002-01-09
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Serial read/write
C365S189011, C365S189020, C710S001000
Reexamination Certificate
active
06661726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to data storage in a data processing system, and in particular to a memory device used as an elastic data transfer interface in a data processing system. Still more particularly, the present invention relates to a memory device that can operate in multiple modes of operation to provide a configurable elastic data transfer interface within a data processing system.
2. Description of the Related Art
Shift registers can be used in parallel to form a first-in, first-out (FIFO) memory. These are typically register memories with independent input and output busses. At the input port, data is controlled by a shift-in clock operating in conjunction with an input ready signal which indicates whether the memory is able to accept further words or is now full. The data entered is automatically shifted in parallel to the adjacent memory location if it is empty, and as this continues, the data words stack up at the output end of the memory. At the output port, data transfers are controlled by a shift-out clock and its associated output ready signal. The output ready signal indicates either that a data word is ready to be shifted out, or that the memory is now empty. FIFOs can easily be cascaded to any desired depth and operated in parallel to give any required word length. This type of memory is widely used in controlling transfers of data between digital subsystems operating at different clock rates, and is often known as an elastic store memory or an elastic data transfer interface.
FIG. 1
is a diagram illustrating a conventional elastic store memory. The elastic store memory shown in
FIG. 1
has addresses,
0
to N where N is an arbitrary number. The write operation and the read operation are separately carried out in the increasing order of address. After the address N is processed, address
0
is processed. Signals used on the write side of the elastic store memory are a Clock
1
, Input Data (write data), Write Inhibit and Write Reset. When the Write Reset signal is applied to the elastic store memory, the Write Address is set to be address
0
. Signals used on the read side of the elastic memory to are a Clock
2
, Output Data (read data), Read Inhibit, Read Reset and phase comparison (PCO). When the Read Reset signal is applied to the elastic store memory, the read address is set to address
0
.
The elastic store memory recognizes valid readout data during the time when data is successively read out from a storage area specified by an address to which the writing of input data is already completed. When the bit rate of the read operation is greater than that of the write operation, there is a possibility that data related to an address for which the writing of new (next) input data has not yet been carried out is read out from a storage location specified by the above address. In other words, the same data is twice read out from the same storage area. On the other hand, when the bit rate of the read operation is less than that of the write operation, there is a possibility that before data is read out from a storage area, new input data is written into the above storage location. In this case, the above data which has not yet been read out is lost. The above-mentioned re-reading of data and lack of data is defined as corruption of data.
Often, an elastic store memory is used in various applications of different frequencies. Rather than design separate elastic buffer designs for these separate applications, it would be desirable to provide a multi-mode elastic buffer that is configurable as an elastic data transfer interface for a selected set of frequencies. Moreover, it would be desirable for such a multi-mode data transfer interface to have the capability to dynamically compensate for discrepancies in the operating frequencies of the two subsystems being interfaced. By dynamically controlling the operation of the elastic data transfer interface to prevent data corruption, system efficiency is increased by reducing memory occupancies of halted input data.
SUMMARY OF THE INVENTION
According to a preferred embodiment, an improved memory device having multiple modes of operation for elastic data transfer is provided. The memory device includes a first elastic store memory containing a plurality of locations, and having a data input receiving write data from a first input data bus, and having a data output that outputs read data from the plurality of locations. A second elastic store memory contains a plurality of locations, and has a data input connected to a first input data bus or a second input data bus as a function of a mode signal, and having a data output that outputs read data from the plurality of locations, wherein the write data and read data are written into and read out from the first and second elastic store memories at a write timing and a read timing, respectively. A write address decoder receives a plurality of write address bits on a write address bus. The write address decoder directs, as a function of the mode signal, that write data received at the data inputs of the first and second elastic store memories is either: (i) alternately written into the first and second elastic store memories within separate address spaces as defined by separate values of the write address bits, or (ii) written into the first and second elastic store memories within the same address space as defined by the write address bits. The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5926643 (1999-07-01), Miura
patent: 6334163 (2001-12-01), Dreps et al.
Aipperspach Anthony Gus
Behrends Derick Gardner
Bracewell & Patterson LLP
Elms Richard
Nguyen Nam
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