Multiple microprocessors with a shared cache

Details Multiple microprocessors with a shared cache Multiple microprocessors with a shared cache

2001-08-17

2004-06-15

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000, C711S137000

Reexamination Certificate

active

06751706

ABSTRACT:

This application claims priority to European Application Serial No. 00402331.3, filed Aug. 21, 2000.
FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in cache memory and access circuits, systems, and methods of making.
BACKGROUND
Microprocessors are general-purpose processors that provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first aspect of the invention, there is provided a digital system having several processors, a private level one (L
1
) cache associated with each processor, a shared level two (L
2
) cache having several segments per entry, and a level three (L
3
) physical memory. The shared L
2
cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L
2
-cache misses, the penalty to access to data within the L
3
memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss.
In another embodiment, a shared translation lookaside buffer (TLB) is provided for L
2
accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L
2
cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task.
In another embodiment, configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.


REFERENCES:
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Texas Instruments Incorporated, S/N: 09/591,537, filed Jun. 9, 2000,Smart Cache.
Texas Instruments Incorporated, S/N: 09/187,118, filed Nov. 5, 1998,Computer Circuits, Systems, and Methods Using Partial Cache Cleaning.
Texas Instruments Incorporated, S/N: 09/447,194, filed Nov. 22, 1999,Optimized Hardware Cleaning Function for VIVT Data Cache.
Texas Instruments Incorporated, S/N: 09/591,656, filed Jun. 9, 2000,Cache With Multiple Fill Modes.

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