Multiple memory standard physical layer macro function

Details Multiple memory standard physical layer macro function Multiple memory standard physical layer macro function

2011-06-28

2011-06-28

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S189050, C365S189140, C365S233130, C365S233160

Reexamination Certificate

active

07969799

ABSTRACT:
A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

REFERENCES:
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patent: 2002/0176309 (2002-11-01), Kwak
patent: 2006/0013060 (2006-01-01), Li et al.
patent: 2006/0174140 (2006-08-01), Harris et al.
patent: 2007/0195613 (2007-08-01), Rajan et al.
patent: 2008/0201597 (2008-08-01), Chong et al.

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