Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-09-18
2007-09-18
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S702000, C257SE21548
Reexamination Certificate
active
11170273
ABSTRACT:
A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the spaces defined by the first mask. A first set of features is etched into the etch mask stack through the sidewall layer. The mask and sidewall layer are removed. An additional feature step is performed, comprising forming an additional mask over the etch mask stack, forming a sidewall layer over the additional mask, etching a second set of features at least partially into the etch mask stack. A plurality of features is etched into the etch layer through the first set of features and the second set of features in the etch mask stack.
REFERENCES:
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4838991 (1989-06-01), Cote et al.
patent: 4857477 (1989-08-01), Kanamori
patent: 5459099 (1995-10-01), Hsu
patent: 5654238 (1997-08-01), Cronin et al.
patent: 5874359 (1999-02-01), Liaw et al.
patent: 5895740 (1999-04-01), Chien et al.
patent: 5981148 (1999-11-01), Brown et al.
patent: 6183937 (2001-02-01), Tsai et al.
patent: 6416933 (2002-07-01), Singh et al.
patent: 6528372 (2003-03-01), Lukanc et al.
patent: 6589713 (2003-07-01), Okoroanyanwu
patent: 6610607 (2003-08-01), Armbrust et al.
patent: 6665856 (2003-12-01), Pierrat et al.
patent: 6955961 (2005-10-01), Chung
patent: 7033948 (2006-04-01), Chung et al.
patent: 2002/0071997 (2002-06-01), Ahrens et al.
patent: 2002/0182549 (2002-12-01), Chang et al.
patent: 2003/0073298 (2003-04-01), Gonzalez et al.
patent: 2003/0232509 (2003-12-01), Chung et al.
patent: 2004/0048170 (2004-03-01), Pierrat et al.
patent: 2004/0180267 (2004-09-01), Tejnil
patent: 2004/0229135 (2004-11-01), Wang et al.
patent: 2005/0048785 (2005-03-01), Kang et al.
patent: 2005/0070111 (2005-03-01), Kushibiki et al.
patent: 2005/0081178 (2005-04-01), Sivakumar et al.
patent: 2006/0011575 (2006-01-01), Chung et al.
patent: 10223249 (2003-12-01), None
patent: 05088375 (1993-04-01), None
U.S. Appl. No. 11/050,985, entitled “Reduction of Feature Critical Dimensions Using Multiple Masks”, by inventors Marks et al., filed Feb. 3, 2005.
U.S. Appl. No. 11/126,466, entitled “Reticle Alignment and Overlay for Multiple Reticle Process”, by inventors Sadjadi et al., filed May 10, 2005.
U.S. Appl. No. 11/126,708, entitled “Computer Readable Mask Shrink Control Processor”, by inventors Sadjadi et al., filed May 10, 2005.
U.S. Appl. No. 11/050,985, entitled “Reduction of Feature Critical Dimensions Using Multiple Masks”, by inventors Marks et al., filed Feb. 3, 2005.
International Search Report and Written Opinion, mailed Jun. 23, 2006.
Office Action dated May 2, 2006, U.S. Appl. No. 11/050,985.
Beyer & Weaver, LLP
Estrada Michelle
Lam Research Corporation
Stark Jarrett J
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