Multiple level storage DRAM cell

Details Multiple level storage DRAM cell Multiple level storage DRAM cell

1996-12-23

1998-06-23

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365168, G11C 1124

Patent

active

057711879

ABSTRACT:
A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

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