Multiple level random access memory

Details Multiple level random access memory Multiple level random access memory

1993-10-15

1995-10-17

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365168, 365206, G11C 1124

Patent

active

054596866

ABSTRACT:
A semiconductor memory device according to the present invention comprises a number of memory cells that store multiple voltage levels. Each voltage level is uniquely assigned to a different logic level. Multiple binary codes are converted to various analog voltage levels by a digital to analog converter. The memory cell of the invention comprises a storage capacitor and transfer gates, each terminal of which is connected to a bit line through the transfer gate for isolating the storage capacitor from the interference of other circuits while it is not accessed. In the writing cycle, analog voltage can be stored in the storage capacitor of each cell by applying the assigned analog voltage generated by the digital to analog converter through, bit lines and the transfer gates that control the conductivity between the bit lines and storage capacitor. In the reading cycle, a stored voltage can be applied to a digital to analog converter by making the transfer gates conductive between the storage capacitor and the bit lines. The invention further comprises a set of transfer gates, which comprises a pair of complementary types of transistors such as n-channel CMOS FET and p-channel CMOS FET, which are connected in a parallel configuration for the purpose of cancelling the gate to channel noise. The set of transfer gates is used in the connection between said storage capacitor and a set of bit lines to reduce the switching noise which limits the possible number of voltage levels in the storage capacitor which corresponds to the number of storable binary codes per unit cell. The pair of transistors similarly configured are also used to discharge the storage capacitor and stray capacitor between the bit lines for reducing noise interference to the storage capacitor.

REFERENCES:
patent: 4661929 (1987-04-01), Aoki et al.
patent: 5184324 (1993-02-01), Ohta
Ishizuka, O., et al. "On Design of Multiple-Valued Static Random-Access-Memory", Proceedings of the Twentieth International Symposium of Multiple-Valued Logic, May 23-25, 1990, Charlotte, N.C., pp. 11-17.

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