Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-04-08
2001-01-30
Everhart, C. (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S688000
Reexamination Certificate
active
06180520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor components and more specifically to the field of integrated circuits. It more particularly relates to the structure and manufacturing of multiple layer connection networks formed on such components.
2. Discussion of the Related Art
An integrated circuit formed on a silicon chip includes various regions with different types of dopings, for example corresponding to drains, sources and gates of MOS transistors. Contacts have to be made on these regions, some of the regions must be interconnected, and access must be provided to output terminals. To solve the interconnect and connection crossing problems, several levels of interconnects have to be made. These interconnect levels are currently called metallizations. It should be noted that the conductive connection components are not always metals but can also be formed from several other conductive materials. In the following description, the expression “metallization level” designates a conductive layer formed at a given stage and etched appropriately. The expression “via” designates a path formed in a insulating layer between two metallization levels and filled with a conductive material to enable localized connections between portions of two separate metallization levels.
Several structures and methods used to construct these metallization layers and vias are known. However, there is a constant need for improvement of these structures and methods due to the increasing miniaturization of integrated circuits. Presently, elementary dimensions lower than 1 &mgr;m are reached. Clearly, structures and methods developed for constructing structures in which the minimal dimensions were higher than one micrometer are no longer adequate and therefore new methods have to be developed. The alterations can sometimes appear to be very slight, but they are of major importance in that they make possible what used to be impossible.
Besides the various problems associated with the proper filling of the vias and the compatibility between materials, the size reduction of integrated circuits particularly increases the acuteness of two particular problems. The first problem lies in the fact that, for large circuits, the stray lateral capacitances between metallization levels dominate the lateral capacitances between portions of a same metallization level, whereas the relationship tends to reverse as the miniaturization increases. The second problem arises because as the miniaturization increases, the number of components formed in a same silicon chip increases and thus the number of connections increases correlatively. As a result, the resistance of the interconnects, the vias and the interconnect/via interfaces becomes a critical problem, in particular when it is desired to have the integrated circuit operate at high frequencies.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a new structure and a new method for manufacturing interconnect networks capable of overcoming the two above-mentioned problems.
Another object of the present invention is to provide a method for manufacturing interconnect levels essentially using individual techniques known per se in the field of the manufacturing of integrated circuits.
To achieve these objects, the present invention provides an interconnect structure wherein the upper surface of the first interconnect level is a tungsten layer, portions of the first interconnect level are insulated from one another by an insulator of the SOG type, portions of a second interconnect level are connected to portions of the first interconnect level by conductive pads formed in openings of an insulating layer, at least the lower part of which is of the SOG type, the walls and the bottom of the openings are covered with a thin titanium layer, and the openings are filled with a conductive material selected in the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys.
According to an embodiment of the present invention, a thin titanium nitride TiN layer is formed under the thin titanium layer.
According to an embodiment of the present invention, the thickness of the titanium layer is lower than 30 nm and preferably lower than 10 nm.
According to an embodiment of the present invention, the thickness of the TiN layer is around ten nanometers
The present invention also provides a method for forming two levels of an interconnect structure including the steps of forming a first interconnect level in a material selected from the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys, etching the first interconnect level according to a selected pattern, covering the structure with an insulating layer, the lower part of which, extending between the portions of the first interconnect level and over the upper surface of the first interconnect level, is in a material of the SOG type, etching openings in the insulating layer which face selected portions of the first interconnect level, depositing a thin titanium layer, forming a second interconnect level and filling the openings by deposition at a temperature higher than 500° C. of a material selected from the group including Al, Cu and aluminum alloys.
According to an embodiment of the present invention, the method further includes the step of depositing on the second interconnect level a thin titanium layer and a thin tungsten layer and etching the second interconnect level according to selected patterns.
According to an embodiment of the present invention, a thin TiN layer is deposited before the thin titanium layer.
According to an embodiment of the present invention, the thickness of the titanium layer is lower than 30 nm and preferably lower than 10 nm.
According to an embodiment of the present invention, the thickness of the TiN layer is around ten nanometers.
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Marty Michel
Passemard G{acute over (e)}rard
Wyborn Graeme
Everhart C.
Galanthay Theodore E.
Morris James H.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
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