Multiple interval single phase clock

Details Multiple interval single phase clock Multiple interval single phase clock

1993-12-23

1995-02-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

3701053, 375373, 327141, 327258, 327295, H04L 704

Patent

active

053944437

ABSTRACT:
A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired. Error detection circuitry is provided to ensure proper operation of the circuitry generating the enable signals.

REFERENCES:
patent: 3921079 (1975-11-01), Heffner et al.
patent: 4654599 (1987-03-01), Zbinden et al.
patent: 4692932 (1987-09-01), Denhez et al.
patent: 4833695 (1989-05-01), Greub
patent: 4847516 (1989-07-01), Fujita et al.
patent: 5133064 (1992-07-01), Hotta et al.

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