Multiple interrupt handling method and apparatus

Details Multiple interrupt handling method and apparatus Multiple interrupt handling method and apparatus

1998-06-01

2001-08-07

Hjerpe, Richard (Department: 2674)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S262000, C710S263000, C710S266000

Reexamination Certificate

active

06272585

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple interrupt handling method and to a corresponding apparatus, more particularly for handling a multiplicity of interrupt requests sent from a multiplicity of interrupt sources to a microprocessor, for instance in a processing unit of a telecommunication system.
2. Background of the Invention
A known method for taking account of an occurring event to be processed by means of a processor requires an interrupt request of the operation then processed to have it restarted later from the stop point as soon as possible after the event accounting.
However such a method does not fit well when there is a need for multiple interrupt handling by means of a same microprocessor as required in some processing systems, knowing that only one interrupt is processed at a time. European Patent Application 0 469 543 relates to a multiple interrupt handling circuit allowing a multiplicity of interrupt requests to be handled without exception in a processor controlled system. The circuit comprises interrupt selecting means associated with interrupt flag registering means and with latching means. It selects one interrupt request among several others simultaneously present for immediate transmission to the processor.
However, in some systems and more specifically real-time handling systems as found in telecommunication, there is a possibility of different interrupt types and/or of a large number of interrupt sources. Handling all interrupt requests would require excessive processing time and/or equipment with the known methods and apparatuses. Such a handling is even useless when the interrupt causes are either redundant or no more significant as it happens in systems, such as alarm systems in which several monitored consequences are often driven from a same action.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for handling interrupt requests generated by a plurality of interrupt sources in a system with a processor, said method including steps of scanning interrupt registering means for determining a current interrupt request to be sent to the processor among interrupt requests having respective interrupt flags inputted in said interrupt registering means, and steps involving the processor for execution of an interrupt processing program according to the result of a comparison of a scanned interrupt flag with a predetermined flag value.
According to the invention, the method includes a step of latching a flag corresponding to a first occurring interrupt request from a source in a group of sources into interrupt latch registering means for further processing and for blocking further interrupt requests from at least the same source in the same group from having a flag latched before processor controlled resetting, this latching step being performed for each other scanned interrupt flag from a different source of a same or different group of sources, upon termination of the interrupt processing program for the interrupt currently in process.
According to the invention, the method also includes a step of comparing the current state for an interrupt source with a previously recorded state for the same interrupt source for generating an interrupt request if and only if the compared states are different
Another object of the present invention is to provide an apparatus for handling interrupt requests generated by a plurality of interrupt sources, said apparatus including means associated with a processor for initiating and executing an interrupt processing program, said means including interrupt flag registering means selecting one current interrupt from a source to be transmitted to the processor among several other current interrupts from other sources.
According to the invention, the apparatus includes latch registering means receiving a first occurring interrupt from a source included in a group of sources and blocking further interrupts from at least the same source in the same group from being latched before processor controlled resetting, said latch registering means including a number of individual latch registering units for interrupt flags far smaller than the number of interrupt sources connected.
According to the invention, the apparatus also includes state recording means associated with sources and comparing means for providing an interrupt request when a current state for a source differs from the state previously recorded for the same source.


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