Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1998-03-17
2000-05-16
Santamauro, Jon
Electronic digital logic circuitry
Interface
Logic level shifting
326 50, 326 71, 327 74, 327333, H03K 190185
Patent
active
060642262
ABSTRACT:
The present invention provides an input receiver in a differential amplifier or modified differential amplifier configuration which adjusts the input high and low voltage signals compatible with multiple input/output (I/O) interfaces, including transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), and Stub Series Terminated Logic (SSTL) interfaces. Transistors in a differential amplifier or modified differential amplifier configuration that receive a reference.sub.-- voltage signal and receiver.sub.-- enable signal are adjusted in accordance to the input high signal and input low signal requirements for a selected type of interface, while other transistors remain at a relatively constant voltage. Once a particular type of interface has been selected, the gate voltages for the transistors that receive the reference.sub.-- voltage and receiver.sub.-- enable signals remain relatively constant. The switching speed of an input receiver is not adversely affected by the additional load of non-operational FETs for one or more of the I/O interface types due to the supply of constant gate voltages to the transistors.
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patent: 5438281 (1995-08-01), Takahashi et al.
patent: 5936429 (1999-08-01), Tomita
Santamauro Jon
Vanguard International Semiconductor Corporation
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