Multiple-input OR-gate employing a sense amplifier

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

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Details

326112, 326108, H03K 19094

Patent

active

055171338

ABSTRACT:
The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss. The feedback element includes a time delay, whereby output signals provided by the second inverter are input to the first inverter subject to a time delay. Both method and apparatus embodiments of the invention are disclosed. Furthermore, a particular circuit embodiment is disclosed.

REFERENCES:
patent: 4728827 (1988-01-01), Woo
patent: 4857764 (1989-08-01), Young
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 4918341 (1990-04-01), Galbraith et al.
patent: 5001367 (1991-03-01), Vinal
patent: 5059828 (1991-10-01), Tanagawa
patent: 5184032 (1993-02-01), Leach
patent: 5408145 (1995-04-01), Nguyen

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