Multiple erase block tagging in a flash memory device

Details Multiple erase block tagging in a flash memory device Multiple erase block tagging in a flash memory device

2006-10-03

2006-10-03

Peikari, B. James (Department: 2189)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S218000, C711S166000, C711S156000, C711S103000

Reexamination Certificate

active

07116584

ABSTRACT:
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

REFERENCES:
patent: 6055184 (2000-04-01), Acharya et al.
patent: 6529416 (2003-03-01), Bruce et al.
patent: 6577540 (2003-06-01), Choi
patent: 6643184 (2003-11-01), Pio
patent: 6735119 (2004-05-01), Mihara

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