1991-02-04
1992-04-28
Larkins, William D.
357 55, H01L 27108
Patent
active
051092590
ABSTRACT:
A multiple DRAM cell trench structure provides increased cell capacitance. A deep trench (18) is formed in a P+ semiconductor substrate (10), with sufficient trench width to prevent the tapered trench sidewalls from pinching off at the bottom thereof. Plural memory cells are formed in the trench (18) to increase the cell density of the array. Field oxide strips (14, 15) are formed between conductive polysilicon bitlines (16, 38) and the P- substrate (12) to reduce capacitance and the soft error rate of the cells.
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Donaldson Richard L.
Kesterson James C.
Larkins William D.
Matsil Ira S.
Texas Instruments Incorporated
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