Multiple data rate synchronous DRAM for enhancing data transfer

Details Multiple data rate synchronous DRAM for enhancing data transfer Multiple data rate synchronous DRAM for enhancing data transfer

1998-12-29

2000-01-18

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 800

Patent

active

06016283&

ABSTRACT:
The present invention relates to a multiple data rate memory device which has broadened the concept of a double data rate SDRAM. The multiple data rate memory device includes clock signal generator means for receiving an external clock of a frequency f and outputting a plurality of clocks, a frequecy multi-doubler for logically operating the plurality of clocks and outputting an internal clock of a frequency 2Nf (N is natural number); an odd data input buffer for receiving tha data at the rising edge of the internal clock; and an even data input buffer for receiving tha data at the falling edge of the internal clock.

REFERENCES:
patent: 5317540 (1994-05-01), Furuyama
patent: 5345573 (1994-09-01), Bowden, III et al.
patent: 5384744 (1995-01-01), Lee
patent: 5473756 (1995-12-01), Traylor
patent: 5648931 (1997-07-01), Obara
patent: 5689213 (1997-11-01), Sher
patent: 5699530 (1997-12-01), Rust et al.
patent: 5844844 (1998-12-01), Bauer et al.

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