Multiple data rate memory interface architecture

Details Multiple data rate memory interface architecture Multiple data rate memory interface architecture

2007-02-13

2007-02-13

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C365S068000

Reexamination Certificate

active

10857396

ABSTRACT:
The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

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