Multiple data rate memory interface architecture

Details Multiple data rate memory interface architecture Multiple data rate memory interface architecture

2011-08-09

2011-08-09

Crawford, Jason (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C365S193000

Reexamination Certificate

active

07994816

ABSTRACT:
The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

REFERENCES:
patent: 5764080 (1998-06-01), Huang et al.
patent: 6279073 (2001-08-01), McCracken et al.
patent: 6664838 (2003-12-01), Talledo
patent: 6742098 (2004-05-01), Halbert et al.
patent: 6806733 (2004-10-01), Pan et al.
patent: 6894531 (2005-05-01), Nouban et al.
patent: 7167023 (2007-01-01), Pan et al.
patent: 7176714 (2007-02-01), Lee et al.
patent: 7234069 (2007-06-01), Johnson
patent: 7504855 (2009-03-01), Lee et al.
patent: 2005/0093594 (2005-05-01), Kim et al.

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