Multiple data rate interface architecture

Details Multiple data rate interface architecture Multiple data rate interface architecture

2005-09-20

2005-09-20

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S046000, C326S047000

Reexamination Certificate

active

06946872

ABSTRACT:
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

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