Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-03-04
2003-08-12
Yo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000
Reexamination Certificate
active
06606364
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to communication systems, and is particularly directed to a new and improved bit synchronizer having only a single a phase locked loop, the bandwidth of which is maintained constant over a relatively wide baud rate range, by making the loop's phase/frequency detector gain constant proportional to the loop's clock divider ratio.
BACKGROUND OF THE INVENTION
In order to recover and synchronize to the embedded clock of a received data communication signal (and thereby accurately sample the received signal to extract the data), digital communication receivers have customarily employed a digitally programmable (numerically controlled) phase locked loop (PLL) of the type shown diagrammatically in FIG.
1
. This standard PLL configuration includes a stable clock signal generator (voltage-controlled oscillator—VCO)
10
, the clock frequency output of which is relatively high compared to the range of data rates capable of being received. The VCO output clock signal is selectively (programmably) divided down by a clock divisor N to a data-rate associated clock frequency by a programmable divider
12
, in order to derive an output clock signal having the same frequency as, and which is to be synchronized with the clock signal embedded in the incoming data signal applied to an input terminal
11
.
The incoming data signal at terminal
11
is coupled to a first input
15
of a phase/frequency detector
16
, a second input
17
of which is coupled to receive the divided-down clock signal from the programmable divider
12
. The phase/frequency detector
16
produces an output that is representative of the phase/frequency differential between the two signals, and couples this output through a loop filter
18
(customarily implemented as an operational amplifier-based circuit) to the VCO
10
. An input data signal DATA may be sampled by means of a flip-flop
19
, which is clocked with the output clock signal from the divider
12
.
Now although the loop parameters of the PLL configuration of
FIG. 1
can be tailored to achieve satisfactory performance over a reasonably narrow bandwidth, such is not the case if the same loop is expected to handle data rates that may vary over multiple orders of magnitude. A principal reason for this shortcoming is the fact that the loop's parameters are based upon the divisor ratio of the clock frequency divider
12
, and will change if the clock divisor N is varied substantially to accommodate a significant change in data rate. Such a variation in the loop parameters means that neither the loop bandwidth nor its damping constant can be maintained constant as required.
Conventional ‘single loop’ proposals to handle this problem have included the use of a complex loop filter configuration, the parameters of which are controllably adjusted (such as through an arrangement of switched resistor networks), when the data rate is to be changed. Alternative ‘multi-loop’ proposals employ a plurality of phase locked loops having respectively different transfer function parameters (e.g., respectively different, ‘fixed’ loop gain constants that are associated with respectively different frequency ‘bins’ of the overall baud range). The signal processing path for the received signal through a selected one of these PLLs is controllably switched in accordance with that portion of the baud range in which the received signal's clock is located. It will be readily appreciated that such conventional multiple data rate bit synchronizers are relatively complex from a circuit implementation standpoint, both in terms of hardware and control software, and are therefore costly to implement and calibrate.
SUMMARY OF THE INVENTION
In accordance with the present invention, such drawbacks of both single loop and multiple loop clock recovery circuits are effectively obviated by a new and improved ‘single loop’ bit synchronizer, the phase/frequency detector of which has a gain constant that is proportional to the loop's clock divider ratio. In accordance with a preferred embodiment of the invention, this gain constant proportionality is readily accomplished by implementing the phase detector to include a (current mirror-based) charge pump that is operative to charge a capacitor with a current that is representative of the frequency difference between the input data signal and the clock signal produced by the loop's clock divider.
By resistor-coupling the loop filter to the capacitor, the loop filter sees a voltage that is proportional to the integral of the phase detector's output current over the symbol period of the received data signal. As the data symbol period is the inverse of the data rate, it effectively corresponds to the ratio of the clock frequency divisor N to the fixed output frequency produced by the VCO, making the gain constant of the phase detector proportional to the clock divisor N. Since loop bandwidth is defined in accordance with the ratio of the phase detector gain constant (which is proportional to N) to the clock divisor N, the contribution of the divisor N is effectively canceled, so that the loop bandwidth can be maintained constant regardless of data rate (which sets N).
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D'Agati Laurence S.
Vaninetti Roy A.
Walley George M.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Harris Corporation
Nguyen Dung X.
Yo Don N.
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