Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-08
2004-07-13
Donghee, Kang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S339000, C257S343000, C257S344000, C257S408000, C257S491000, C257S492000, C257S493000, C257S494000
Reexamination Certificate
active
06762456
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of lateral RF MOS devices. More specifically, the present invention relates to a lateral MOS structure utilized to build an RF MOS device with an improved hot carrier reliability and improved RF performance.
2. Discussion of the Prior Art
An LDMOS technology is rapidly becoming the technology of choice for RF power amplification in wireless communication applications. There has been a continuous effort to further improve the device performance based on RF LDMOS technology, including optimization in layout and reduction in the gate resistance. However, the device performance remains limited by the large parasitic feedback capacitance C
rss
because the RF output power decreases drastically with the increased parasitic feedback capacitance C
rss
, and parasitic source resistance and inductance. Thus, the reduction of the parasitic feedback capacitance C
rss
, and parasitic source resistance and inductance are crucial to an RF LDMOS device performance.
Another issue is the hot-carrier effects that degrade the performance of an LDMOS device used as an RF power amplifier. Indeed, in such a device, gate and drain may be biased with a high voltage simultaneously. Therefore, the LDMOS device might be forced to operate at high electric field while carrying high current. However, due to the hot-electron injection into the gate oxide, threshold voltage and transconductance change result in the decrease of drain current-carrying capability. Thus, hot-electron effects cause the device gain to decrease and R
Drain-Source
to increase thus resulting in output power degradation.
A number of structures have been proposed in the past years regarding improvements to the performance of LDMOS devices used in RF amplification for wireless applications. All these prior art structures had in common the mininization of parasitic source resistance and inductance, the increase of drain-source breakdown voltage, the maximization of drain current, and the reduction of hot electron carrier effects.
For instance, in the paper “RF LDMOS with Extreme Low Parasitic Feedback Capacitance and High Hot-Carrier Immunity” given by Shuming Xu, Pangdow Foo, Jianqing Wen, Yong Liu, Fujiang Lin, and Changhong Ren at the International Electron Devices Meeting in Washington, D.C., Dec. 5-8, 1999, a new RF LDMOS was demonstrated with a cost effective process technology. By combining a step LDD and an inherent thermal oxide spacer, the parasitic feedback capacitance was reduced by 40%, achieving a 35% higher output power. The hot-electron resistance was also improved by 70%, allowing power to be obtained with a higher reliability.
However, this approach entails the control of the lateral oxidation of the polysilicon gate finger which is difficult to achieve. A simpler approach is to optimize the depth and concentration of the enhanced drain structures in order to maximize the drain-source breakdown voltage, and to minimize the hot electron effects.
An LDMOS device structure with a plug formed on a partially filled trench has another drawback. Indeed, such a structure does not allow one to substantially planarize the LDMOS device structure. This issue is important because a planarized LDMOS structure can be used to increase the degree of freedom in designing an RF LDMOS amplifier device with the required characteristics. For instance, the substantially planarized LDMOS structure can be used to design an RF LDMOS high power amplifier device with an improved RF gain, improved collector efficiency, and a wider usable bandwidth (BW) as compared with an RF LDMOS devices designed by using a conventional non-planarized LDMOS structure.
What is needed is a substantially filled multiple conductive plug LDMOS structure with a reduced hot carrier vulnerability that would allow one to design an RF LDMOS device with an improved RF performance.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides a substantially planarized multiple conductive plug LDMOS structure with a multiple enhanced drain drift region. The LDMOS structure of the present invention allows one design an RF LDMOS power amplifier for wireless applications with substantially improved RF performance because of significantly reduced hot carrier vulnerability and improved drain-source breakdown voltage.
One aspect of the present invention is directed to a lateral RF MOS transistor with at least one conductive plug structure.
In one embodiment of the present invention, the lateral RF MOS transistor with at least one conductive plug structure comprises: (a) a semiconductor material of the first, P conductivity type, or an epi layer, having a first (epi layer) dopant concentration and a top surface; (b) a conductive gate overlying the top surface of the epi layer and insulated from the epi layer by silicon dioxide; (c) a first enhanced drain drift region of the second, N conductivity type, having a second dopant concentration, formed in the epi layer and extended at a first depth level inside the epi layer; (d) a second enhanced drain drift region of N conductivity type, having a third dopant concentration, formed in the epi layer and extended at a second depth level inside the epi layer; (e) a drain region of N conductivity type, having a drain dopant concentration and formed in the epi layer; (f) a body region of P conductivity type, having a body region dopant concentration, including a first end underlying the conductive gate, formed in the epi layer; (g) a source region of N conductivity type formed in the epi layer, having a source region dopant concentration, located within the body region; (h) a body contact region of P conductivity type, having a body contact region dopant concentration, contacting the body region; and (I) a plug region. In one embodiment, the drain region contacts the second enhanced drain drift region, and the second enhanced drain drift region contacts the first enhanced drain drift region.
In one embodiment of the present invention, the plug region further comprises at least one conductive plug region formed in the epi layer, and at least one between-conductive-plug region of the first, P conductivity type, having a between-conductive-plug dopant concentration formed in the epi layer. The conductive plug region contacts the body contact region of the epi layer, and the between-conductive-plug region contacts the conductive plug region.
In one embodiment of the present invention, the plug region further comprises two conductive plug regions formed in the epi layer, and at least one between-conductive-plug region of P conductivity type formed in the epi layer and located between two conductive plug regions. The first conductive plug region contacts the body contact region of the epi layer.
In one embodiment, both the first conductive plug region and the second conductive plug region connect the body contact region of the epi layer to a highly conductive substrate of the structure.
In one embodiment of the present invention, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region, and the drain region dopant concentration is higher than the dopant concentration of the second enhanced drain drift region. In one embodiment of the present invention, the body region dopant concentration is at least equal to the dopant concentration of the epi layer, and the body contact region dopant concentration is greater than the body region dopant concentration.
In one embodiment of the present invention, the first (and/or the second) conductive plug comprises: a metal plug, a silicided plug, a tungsten silicide plug, a titanium silicide plug, a cobalt silicide plug, and/or a platinum silicide plug.
REFERENCES:
patent: 4890146 (1989-12-01), Williams et al.
patent: 5841166 (1998-11-01), D'Anna et al.
D'Anna Pablo
Yan Alan Lai-Wai
Donghee Kang
Sirenza Microdevices, Inc.
Tankhilevich Boris G.
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