Multiple chip assembly

Details Multiple chip assembly Multiple chip assembly

1998-07-21

1998-12-29

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257685, 257706, 257778, H01L 2302

Patent

active

058545077

ABSTRACT:
This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than the associated chip. Each substrate thus has a free area, not masked by the chip, which is utilized to mount a vertically-adjacent substrate. Within this free area, solder balls connect the substrates to provide for vertical logic bus propagation through the assembly and vertical heat dissipation. The solder balls are made to have a relatively low melting temperature, permitting interconnection between chip/substrate layers without affecting connection between chip and substrate or with an intervening carrier. At the same time, the layers are compressed together during such interconnection to bring a thermal transport layer in contact between the bottom of each substrate and the chip of an underlying layer, to facilitate lateral heat dissipation.

REFERENCES:
patent: 5594275 (1997-01-01), Kwon et al.
patent: 5715144 (1998-02-01), Ameen et al.
patent: 5751060 (1998-05-01), Laine et al.
patent: 5760478 (1998-06-01), Bozso et al.

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