Multiple cache coherency

Details Multiple cache coherency Multiple cache coherency

2006-04-18

2006-04-18

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000, C711S141000

Reexamination Certificate

active

07032077

ABSTRACT:
A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.

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