Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-04-28
2002-02-19
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S148000, C711S149000, C711S150000, C710S240000, C710S241000, C712S245000
Reexamination Certificate
active
06349370
ABSTRACT:
BACKGROUND OF THE INVENTION
1
. Field of the Invention
The present invention relates to a parallel processor comprising a plurality of processor elements and a shared memory connected via a common bus and to a processing method thereof.
2
. Description of the Related Art
In recent years, parallel processors have been developed which execute in parallel a plurality of simultaneously executable instructions in a program by a plurality of processor elements (PE) built into a single chip so as to shorten the execution time for the program.
A variety of architectures are being proposed for such parallel processors. Among them, there is one in which a plurality of processor elements and a shared memory are connected to a set of common buses.
FIG. 16
is a view of the system configuration of a general parallel processor
1
of the related art.
As shown in
FIG. 16
, the parallel processor
1
has built into one chip a common bus
2
, n number of processor elements
3
1
to
3
n
, a shared memory
4
, and a bus unit
5
. The common bus
2
has connected to it the processor elements
3
1
to
3
n
, the shared memory
4
, and the bus unit
5
. The bus unit
5
is connected to a main memory
7
via an external chip interface
6
. One data port I/O is provided in a memory cell region
4
a
of the shared memory
4
.
In the parallel processor
1
, data is transferred via the common bus
2
and the data port I/O when the processor elements
3
1
to
3
n
access the data stored in the shared memory
4
.
Summarizing the problem to be solved by the invention, in the above parallel processor
1
, the data transfer between the processor elements
3
1
to
3
n
and the shared memory
4
and the data transfer between the shared memory
4
and the main memory
7
are both carried out via the common bus
2
. Furthermore, since the memory cell region
4
a
of the shared memory
4
has only one data port I/O, there Is the disadvantage that the waiting time of the processor elements
3
1
to
3
n
may frequently become long for the following reasons.
Namely, when a page fault occurs in the shared memory
4
and the pages are being exchanged between the shared memory
4
and the main memory
7
, the processor elements
3
1
to
3
n
cannot access the shared memory
4
because the common bus
2
is in use. Accordingly, an access request from the processor elements
3
1
to
3
n
to the shared memory
4
ends up being kept waiting until the completion of the page exchange processing and the processing performance of the parallel processor
1
becomes low.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a parallel processor which can realize a high processing performance and method of the same.
According to a first aspect of the present invention, there is provided a parallel processor comprising: a plurality of processor elements each having an inner memory storing one or more sub-pages and performing signal processing for the data stored in the inner memory; a first bus connected to the plurality of processor elements; a second bus connected to an outer memory; and a shared memory connected to the first bus and the second bus, the shared memory comprising: a storage means for storing a plurality of sub-pages and a control means for controlling, in accordance with an access request from the processor element, a transfer of a sub-page between the inner memory of the processor element and the storage means via the first bus and a transfer of a page comprising a plurality of sub-pages between the storage means and the outside memory via the second bus, the control means transferring sub-pages by a first access request which is a request accompanied with a page fault from one processor element to the storage means and a second access request which is a request accompanied with a page fault from another processor element to the storage means from the outside memory to the storage means, and transferring another sub-page of the pages to which the sub-pages by the first access request and the second access request belong from the outside memory to the storage means, when, before the end of a page transfer between the shared memory and outside memory through the second bus due to the first access request, the second access request is generated.
Preferably, the control means transfers sub-pages requested by the first access request and the second access request through the second bus from the outside memory to the storage means, and transfers another sub-page of the page to which the sub-page requested by the first access request belongs through the second bus from the outside memory to the storage means, then transfers another sub-page of the page to which the sub-page requested by the second access request belongs through the second bus from the outside memory to the storage means.
Preferably, the control means transfers the sub-page requested by the first access request through the second bus from the outside memory to the storage means, and transfers the sub-page through the first bus from the storage means to the processor element generating the first access request.
Preferably, the control means transfers the sub-page requested by the second access request through the second bus from the outside memory to the storage means, and transfers the sub-page through the first bus from the storage means to the processor element generating the second access request.
Preferably, the transfer of the sub-page through the first bus and the transfer of the sub-page through the second bus are performed in parallel.
Preferably, the control means is provided with an access request storage unit for storing the first access request and the second access request, a save procedure storage unit for storing a procedure indicating processing for transferring another sub-page of the pages to which the sub-pages by the first access request and the second access request belong from the outside memory to the storage means, and a control unit for storing in the save procedure storage unit a first procedure for transferring another sub-page of the page to which the sub-page by the first access request belongs through the second bus from the outside memory to the storage means, storing in the save procedure storage unit a second procedure for transferring another sub-page of the page to which the sub-page by the second access request belongs through the second bus from the outside memory to the storage means, calling up and executing the first procedure from the save procedure storage unit, and calling up and executing the second procedure from the save procedure storage unit after execution of the first procedure.
Preferably, the control means is provided with an access request storage unit for storing the first access request and the second access request in correspondence with save data and a control unit for transferring the sub-page by the first access request through the second bus from the outside memory to the storage means; setting the save data corresponding to the first access request stored in the access request storage unit in a save state, transferring the sub-page requested by the second access request through the second bus from the outside memory to the storage means, setting the save data corresponding to the second access request stored in the access request storage unit in the save state, using the save data to read the first access request stored in the access request storage unit, transferring another sub-page of the page to which the sub-page requested by the first access request belongs through the second bus from the outside memory to the storage means, using the save data after the transfer to read the second access request stored in the access request storage unit, and transferring another sub-page of the page to which the sub-page by the second access request belongs through the second bus from the outside memory to the storage means.
Preferably, the storage means is provided with a plurality of sub-banks each storing one sub-page and the shared memory further comprises a plurality of s
Kananen Ronald P.
Nguyen Than
Rader & Fishman & Grauer, PLLC
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