Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2007-10-16
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10957261
ABSTRACT:
Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates. When separate test bitstreams are used, the configuration procedure programs the IC with an associated user bitstream before terminating.
REFERENCES:
patent: 4899067 (1990-02-01), So et al.
patent: 5153880 (1992-10-01), Owen et al.
patent: 5255227 (1993-10-01), Haeffele
patent: 5349248 (1994-09-01), Goetting et al.
patent: 5430734 (1995-07-01), Gilson
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5459342 (1995-10-01), Nogami et al.
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5513144 (1996-04-01), O'Toole
patent: 5592102 (1997-01-01), Lane et al.
patent: 5742556 (1998-04-01), Tavrow et al.
patent: 5761483 (1998-06-01), Trimberger
patent: 5764577 (1998-06-01), Johnston et al.
patent: 5777887 (1998-07-01), Marple et al.
patent: 5796750 (1998-08-01), Lottridge et al.
patent: 5925920 (1999-07-01), MacArthur et al.
patent: 6003150 (1999-12-01), Stroud et al.
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6166559 (2000-12-01), McClintock et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6201404 (2001-03-01), Reddy et al.
patent: 6202182 (2001-03-01), Abramovici et al.
patent: 6289292 (2001-09-01), Charlton et al.
patent: 6292925 (2001-09-01), Dellinger et al.
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6496971 (2002-12-01), Lesea et al.
patent: 6530071 (2003-03-01), Guccione et al.
patent: 6560740 (2003-05-01), Zuraski, Jr. et al.
patent: 6618686 (2003-09-01), Allamsetty
patent: 6664808 (2003-12-01), Ling et al.
patent: 6681353 (2004-01-01), Barrow
patent: 6725442 (2004-04-01), Cote et al.
patent: 6915503 (2005-07-01), Lesea
patent: 6918027 (2005-07-01), Mantey et al.
patent: 6925407 (2005-08-01), Duppong
patent: 7007250 (2006-02-01), Bapat et al.
patent: 7071679 (2006-07-01), Sabih et al.
patent: 7080300 (2006-07-01), Herron et al.
patent: 7127697 (2006-10-01), Wells et al.
patent: 7146598 (2006-12-01), Horanzy
patent: 7185293 (2007-02-01), Ofer
patent: 2001/0037458 (2001-11-01), Kean
patent: 2003/0097551 (2003-05-01), Fuller et al.
patent: 2003/0212940 (2003-11-01), Wong
patent: 2003/0225955 (2003-12-01), Feldstein et al.
patent: 2004/0010739 (2004-01-01), Odom et al.
patent: 2004/0193979 (2004-09-01), Avery et al.
patent: 2004/0193980 (2004-09-01), Avery et al.
patent: 2005/0125512 (2005-06-01), Fuller et al.
patent: 2005/0177251 (2005-08-01), Duppong
patent: 2005/0245098 (2005-11-01), Cooney et al.
patent: 2005/0246520 (2005-11-01), Vadi et al.
patent: 2006/0253266 (2006-11-01), Ong
patent: 2006/0259871 (2006-11-01), Washington et al.
U.S. Appl. No. 10/085,305, filed Feb. 28, 2002, Trimberger.
U.S. Appl. No. 10/104,324, filed Mar. 22, 2002, Wells et al.
U.S. Appl. No. 10/714,380, filed Oct. 31, 2003, Trimberger.
U.S. Appl. No. 10/717,040, filed Nov. 18, 2003, Ngai et al.
U.S. Appl. No. 10/813,414, filed Mar. 26, 2004, Stassart et al.
John Emmert et al.; “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration”; Annual IEEE Symposium on Field-Programmable Custom Computing Machines; Apr. 17, 2000; pp. 165-174.
John M. Emmert et al.; “Incremental Routing in FPGAs”; ASIC Conference 1998. Proceedings, Eleventh Annual IEEE International; Rochester, NY; Sep. 13-16, 1998; pp. 217-221.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Dec. 6, 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 33-75.
W. Bruce Culbertson et al.; “Defect Tolerance on the Teramac Custom Computer”; The 5th Annual IEEE Symposium on Field-Programmabel Custom Computing Machines; Apr. 16-18, 1997; pp. 116-123.
Fran Hanchek et al.; “Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs”; The Proceedings of the Ninth International Conference on VLSI Design; Jan. 1996; pp. 1-4.
Altera; Altera Data Sheet, vol. 1, Chapter 3 “Configuration and Testing”; and vol. 2 Chapter 8 “Remote System Upgrades with Stratix II Devices”; Feb. 2004; downloaded on Jun. 17, 2004 freom http://www.altera.com/literature/lit-stx2.
U.S. Appl. No. 10/956,556, filed Oct. 1, 2004, Trimberger.
U.S. Appl. No. 10/956,986, filed Oct. 1, 2004, Trimberger.
U.S. Appl. No. 10/956,990, filed Oct. 1, 2004, Trimberger.
Cartier Lois D.
Do Thuan
Xilinx , Inc.
LandOfFree
Multiple bitstreams enabling the use of partially defective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple bitstreams enabling the use of partially defective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple bitstreams enabling the use of partially defective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3902517