Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-23
2003-12-30
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S311000
Reexamination Certificate
active
06670669
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a novel non-volatile memory capable of recording multiple bit information in a single memory cell having a non-conductive charge trapping gate.
BACKGROUND ART
Non-volatile memories that utilize semiconductor are in widespread use as information recording media on account of being capable of retaining information even if the power supply is OFF, and being capable of read-out at high speeds. In recent years, non-volatile memories have been employed in mobile information terminals, and as recording media for digital cameras and for digital music in the form of MP3 data, for example.
Non-volatile memories, such as the flash memories that are currently in widespread use, are constructed so as to have a conductive floating gate and control gate on a channel region between a source region and drain region. A non-volatile memory of this kind is constituted such that a floating gate is buried in a gate insulating film, and one-bit information is stored according to whether charge is or is not injected into this floating gate. Due to the fact that these non-volatile memories of widespread usage have a floating gate that is electrically conductive, when defects, however small, are present in the gate oxide film, electrons in the floating gate are all lost via these defects. There is therefore a problem in that high reliability is unattainable.
Other than the non-volatile memories of widespread usage mentioned above, a new type of non-volatile memory has been proposed that is provided with a non-conductive charge trapping gate in place of a floating gate, and that stores two-bit information by causing charge beside the source and beside the drain to be trapped. For example, a non-volatile memory of this kind is disclosed in the PCT application W099/07000 “Two Bit Non-volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”. Since this non-volatile memory has a trapping gate that is non-conductive, the probability of loss of electrons injected locally is low, whereby it is possible to attain high reliability.
FIG. 1
shows the constitution of the above-mentioned conventional two-bit non-volatile memory. FIG.
1
(
1
) is a cross-sectional view thereof, and FIG.
1
(
2
) is an equivalent circuit diagram thereof. Source-drain regions SD
1
, SD
2
are formed at the surface of a silicon substrate
1
, and a trapping gate TG formed from a silicon nitride film or the like, and a control gate CG of a conductive material, are formed on the channel region. The trapping gate TG is buried in the insulating film
2
made of silicon oxide film or the like, to thereby form a composite MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure. By utilizing the difference in bandgap between the silicon nitride film and silicon oxide film, it is possible to cause charge to be trapped and retained in the silicon nitride film.
The special constitution of this non-volatile memory is a trapping gate TG consisting of a non-conductive substance such as a dielectric material, for example, and, in a case in which charge is injected into this trapping gate TG, charge within the trapping gate is unable to move. As a result, it is possible to make a distinction between a case in which charge is injected in the vicinity of the first source-drain region SD
1
, and a case in which charge is injected in the vicinity of the second source-drain region SD
2
, and it is thus possible to record two-bit data.
FIG.
1
(
2
) is an equivalent circuit diagram for the above-mentioned two-bit non-volatile memory. Since the trapping gate TG is non-conductive, this trapping gate TG is equivalent to a constitution in which separate MOS transistors are respectively formed in a first trapping gate region TSD
1
in the vicinity of the first source-drain region SD
1
, and in a second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
. Further, in the course of the above-described read-out and programming (write) operations, the first and second source-drain regions SD
1
, SD
2
are used either as source regions or drain regions, and these source-drain regions SD
1
, SD
2
are therefore referred to, in this specification, as the first source-drain region SD
1
and the second source-drain region SD
2
, respectively.
FIG. 2
illustrates programming, erasure and read-out of a conventional two-bit non-volatile memory. The voltage applied to the first source-drain region SD
1
is called as V(SD
1
), the voltage applied to the second source-drain region SD
2
is called as V(SD
2
), and the voltage applied to the control gate is called as Vg.
As shown in FIG.
2
(
1
), the programming (write) of the non-volatile storage memory is executed by applying voltages Vg=10V, V(SD
1
)=0V, V(SD
2
)=6V, for example, to inject hot electrons produced in the vicinity of the second source-drain region SD
2
into the second trapping gate region TSD
2
close to the second source-drain region SD
2
.
In addition, in the course of an erase operation, the voltage applied to the control gate CG is such that Vg=−5V, and 5V is applied to the first or second source-drain region SD
1
or SD
2
, or to both the first source-drain region SD
1
and the second source-drain region SD
2
, to extract electrons from the trapping gate TG by utilizing the FN tunnel effect (the Fowler-Nordheim Tunnel effect). At the same time, hot holes produced in the vicinity of the source-drain regions SD
1
and SD
2
, are injected into the trapping gate TG, so that the charge is neutralized within the trapping gate TG.
Next, the read-out operation involves the application of a voltage, whose bias is the reverse of the voltage of the programming operation, between the first and second source-drain regions SD
1
, SD
2
, to detect whether or not electrons are trapped in the second trapping gate region TSD
2
. In other words, in order to read out the state of the second trapping gate region TSD
2
, voltages applied are Vg=3V, V(SD
1
)=1.6V, V(SD
2
)=0V, for example. Here, as shown in FIG.
2
(
3
), when electrons are present in the second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
, the channel below the gate does not extend so as to touch the second source-drain region SD
2
, and, consequently, a channel current does not flow (
0
data storage state). Conversely, as shown in FIG.
2
(
4
), when electrons are not present in the second trapping gate region TSD
2
in the vicinity of the second source-drain region SD
2
, the channel reaches to the second source-drain region SD
2
, and, consequently, a channel current flows (
1
data storage state). It is thus possible to detect whether or not there is an accumulation of electrons in the second trapping gate region TSD
2
, by detecting the ON and OFF of a cell transistor, that is, the existence of a current.
Furthermore, in read-out of the non-volatile storage memory, when, as shown in FIG.
2
(
5
), voltages applied are: Vg=3V, V(SD
1
)=0,V(SD
2
)=1.6V, i. e. when the voltage application state between the first and second source-drain regions is the reverse of that in FIG.
2
(
3
) mentioned above, even if electrons are, for example, present in the second trapping gate region TSD
2
, the state is the same as a MOS transistor whose channel is pinched off, and a channel current flows. Therefore, in a voltage application state of this kind, it is possible to detect whether or not there is an accumulation of electrons in the first trapping gate region TSDL in the vicinity of the first source-drain region SD
1
, irrespective of the existence of electrons in the second trapping gate region TSD
2
.
As described above, a conventional memory is capable of recording two-bit information by means of the accumulation or non-accumulation of electrons in the nitride film region TSD
1
in the vicinity of the first source-drain region SD
1
and in the nitride film region TSD
2
in the vicinity of the second source-drain
Elms Richard
Fujitsu Limited
Smith Brad
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