Multiple-bank memory architecture and systems and methods using

Details Multiple-bank memory architecture and systems and methods using Multiple-bank memory architecture and systems and methods using

1995-10-26

1997-11-11

Dinh, Son T.

Static information storage and retrieval

Addressing

Plural blocks or banks

365221, 36523004, G11C 800

Patent

active

056871325

ABSTRACT:
A memory 20 is disclosed including a first column of memory cells including a conductive bitline 202 and a second column of memory cells also including a conductive bitline 202. A gate 203 is provided for selectively coupling the bitline 202 of the first column with the bitline 202 of the second column for transferring a bit of data from a selected cell of the first column to a selected cell of the second column.

REFERENCES:
patent: 4893281 (1990-01-01), Hashimoto
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5121360 (1992-06-01), West et al.
patent: 5305284 (1994-04-01), Iwase
patent: 5319603 (1994-06-01), Watanabe et al.
patent: 5377154 (1994-12-01), Takasugi
patent: 5390139 (1995-02-01), Smith et al.

Affiliated with

Also associated with

Rating

Multiple-bank memory architecture and systems and methods using does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple-bank memory architecture and systems and methods using , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple-bank memory architecture and systems and methods using will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1234261