Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-14
2001-11-20
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S074000
Reexamination Certificate
active
06320228
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices. More particularly, the present invention relates to a multiple active layer integrated circuit structure and a method of manufacturing such a structure.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as, processors, non-volatile memory, and other circuits include semiconductor elements, such as, metal oxide semiconductor field effect transistors (MOSFETS), diodes, resistors, and capacitors. For example, flash memory devices employ millions floating gate FETs and processors employ millions of complementary MOSFETS. MOSFETS are generally disposed in active regions disposed in a base layer or substrate. Active regions typically include heavily doped silicon or other semiconductor regions. The regions can be doped with impurities, such as, phosphorous (P), boron (B), arsenic (As), or other material.
Semiconductor elements, such as, floating gate transistors and FETS, are generally bulk semiconductor-type devices in contrast to semiconductor-on-insulator-type devices, such as, silicon-on-insulator (SOI) devices. The floating gate transistors and FETs are disposed in a single plane (single active layer) on a top surface of a semiconductor substrate, such as, a single crystal silicon substrate.
In bulk semiconductor-type devices which have lateral FETs, the top surface of the substrate is doped to form source and drain regions, and a conductive layer is provided on the top surface of the semiconductor substrate between the source and drain regions to operate as a gate. In floating gate FETS, the gate is provided over a floating gate. The number of layers of lateral FETs is limited to one layer (e.g., the top surface) because only one active region is available in conventional planar processes. Additionally, the anisotropic nature of the top surface of the silicon substrate due to the conductive layer limits the number of metal layers and insulative layers which can be provided over the lateral FETs. Thus, in bulk semiconductor type devices, circuit density is limited by the integration density of electrical components on the surface of the wafer (substrate).
The use of only a single active layer can waste valuable silicon material. Bulk-type semiconductor devices utilizing multiple layers have been proposed to reduce the cost of integrated circuits and more efficiently utilize substrate area. These proposed devices utilize seeded epitaxial layers or recrystalized amorphous silicon layers to form multiple layers.
Bulk semiconductor-type devices can be subject to some disadvantageous properties, such as, less than ideal subthreshold voltage slope during operation, high junction capacitance, and ineffective isolation. Additionally, bulk semiconductor-type devices often require epilayers, P-wells, or N-wells which require additional fabrication steps.
Semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator) devices have significant advantages over bulk semiconductor-type devices, including near ideal subthreshold voltage slope, elimination of latch-up, low junction capacitance, and effective isolation between devices. SOI-type devices generally completely surround a silicon or other semiconductor substrate with an insulator. Devices, such as, conventional FETs or other transistors, are disposed on the silicon by doping source and drain regions and by providing gate conductors between the source and drain regions. SOI devices provide significant advantages, including reduced chip size or increased chip density because minimal device separation is needed due to the surrounding insulating layers. Additionally, SOI devices can operate at increased speeds due to reduction in parasitic capacitance. These advantages are particularly important as integration technologies reach sub-100nanometer levels for CMOS devices.
Conventional SOI devices generally have a floating substrate (the substrate is often totally isolated by insulating layers). Accordingly, SOI devices are subject to floating substrate effects, including current and voltage kinks, thermal degradation and large threshold voltage variations. SOI devices also can have some limited packing densities because they are limited in vertical integration. Generally, SOI devices can include a very thin (200-800 Å thick) silicon film separated from a bulk substrate by a thick buried oxide (2000-3000 Å thick). However, the thin silicon film is generally the only active layer.
SOI devices utilizing multiple layers have also been proposed. Multiple layers in these devices are achieved by stacking SOI wafers on top of each other.
Thus, there is a need for an SOI or bulk semiconductor device which has improved density and improved vertical integration. Further, there is a need for an SOI device which includes more than one active layer. Further still, there is a need for method of manufacturing an SOI or bulk semiconductor device including more than one active layer. Yet further, there is a need for a multi-layer device which has some of the advantages of SOI devices without utilizing multiple SOI wafers.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to an integrated circuit. The integrated circuit includes a first semiconductor-on-insulator layer which includes a first active layer, a second active layer, and a third insulating layer. The first semiconductor-on-insulator layer also includes a first insulator layer and a second insulating layer. The first active layer contains a first channel region, and the second active layer includes a second channel region. The second active layer is attached to the second insulating layer, and the third insulating layer is disposed above the second active layer.
Another embodiment relates to a multi-layer structure for containing a plurality of transistors. The multi-layer structure includes a first layer which includes a first semiconductor substrate, a buried oxide layer, and a first active layer. The multilayer structure also includes an insulation layer and a second active layer disposed above the first active layer. The first active layer is disposed below the first insulating layer. The second active layer is bonded to the first insulating layer.
Yet another embodiment relates a method of making a multilayer structure for containing a plurality of transistors. The method includes providing a first layer, attaching a second semiconductor substrate, separating the semiconductor substrate, and doping the second semiconductor substrate to form an active layer. The first layer includes a first semiconductor substrate, a buried oxide layer, and a first active layer. A first insulating layer is provided over the first active layer. The second semiconductor substrate is attached to the first insulating layer. The second semiconductor substrate is separated from the first insulating layer to leave a portion of the second semiconductor substrate attached to the first layer. The portion of the second semiconductor substrate is doped to form the second active layer.
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Ngo Ngan V.
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