Multipath processor with dedicated buses

Details Multipath processor with dedicated buses Multipath processor with dedicated buses

2004-12-21

2008-09-09

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S010000

Reexamination Certificate

active

07424638

ABSTRACT:
A device includes a processor (1) having two states (111, 112) each storing a processing path, a central unit (11) processing the paths in those states, at least one transfer bus (13) between the processor and peripherals, at least one processing path backup and restore bus (14), distinct from the data bus, and a backup and restore memory (15). A processing path controller (16) controls the transfer of a processing path between the memory and a state while the processor processes the processing path of another state. This allows for a reduction in the time wasted by the controller on restore or backup transfers.

REFERENCES:
patent: 5604740 (1997-02-01), Pinault et al.
patent: 5778243 (1998-07-01), Aipperspach et al.
patent: 5812553 (1998-09-01), Pinault et al.
patent: 6006293 (1999-12-01), Thomas
patent: 6223208 (2001-04-01), Kiefer
patent: 6272616 (2001-08-01), Fernando et al.
patent: 6278959 (2001-08-01), Alferness
patent: 7015916 (2006-03-01), Sasaki et al.
patent: 7272674 (2007-09-01), Nandi et al.
patent: WO 03/088036 (2003-10-01), None
Preliminary Search Report, FR 03 15573, dated Jul. 7, 2004.

Affiliated with

Also associated with

Rating

Multipath processor with dedicated buses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multipath processor with dedicated buses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multipath processor with dedicated buses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3982600