Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1996-10-08
1999-01-26
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438153, 438199, 438588, H01L 2100
Patent
active
058638180
ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor. The inverted, upper level transistor thereby comprises a gate conductor residing in an elevation level below the gate dielectric and source/drain implants of that transistor. Direct coupling of one transistor gate conductor to another transistor gate conductor not only minimizes the overall routing between those conductors for the benefit of a high performance circuit, but also is particularly attuned to inverter circuits which utilize mutually connected gate conductors.
REFERENCES:
patent: 4603468 (1986-08-01), Lam
patent: 4654131 (1987-03-01), Miller et al.
patent: 4686758 (1987-08-01), Liu et al.
patent: 5214295 (1993-05-01), Manning
patent: 5334682 (1994-08-01), Manning et al.
patent: 5348899 (1994-09-01), Dennison et al.
patent: 5411909 (1995-05-01), Manning et al.
patent: 5616934 (1997-04-01), Dennison et al.
S. Wolf & R.N. Tauber, "Silicon Processing for the VLSI Era" vol. I, p. 195, 1986.
S. Wolf, "Silicon Processing for the VLSI Era" vol. II, pp. 393-399, 1990.
S. Wolf "Silicon Porcessing for the VLSI Era" vol. II, pp. 144-147, 572-581, Jun. 1990.
Garnder Mark I.
Kadosh Daniel
Paiz Robert
Advanced Micro Devices , Inc.
Daffer Kevin L.
Kowert Robert C.
Nguyen Tuan H.
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