Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2006-07-04
2006-07-04
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S101000
Reexamination Certificate
active
07073040
ABSTRACT:
In one embodiment, a multilevel segmented memory device may be used to store persistent data in a first memory level and dynamic data in a second memory level. In the first level, data fragments may grow in an ascending order, and sequence tables may grow in a descending order. In the second level, object pointers may grow in a descending order, and data units grow in an ascending order.
REFERENCES:
patent: 6842823 (2005-01-01), Olson
patent: 6907508 (2005-06-01), Dearth et al.
patent: 2002/0147900 (2002-10-01), Tashiro et al.
patent: 2003/0110361 (2003-06-01), Kanehira et al.
patent: 2004/0044849 (2004-03-01), Stence et al.
Andrew S. Tanenbaum and Albert S. Woodhull, Operating Systems—Design and Implemention, 1997, 2nd Edition, pp. 343-356.
Sahni, Data Structures, Algorithms, and Applications in Java, 2000, pp. 190, 191, 204.
Bragdon Reginald
Gu Shawn
Intel Corporation
Trop Pruner & Hu P.C.
LandOfFree
Multilevel segmented memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilevel segmented memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel segmented memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3598960