Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-05-29
2007-05-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S757000
Reexamination Certificate
active
10771823
ABSTRACT:
A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.
REFERENCES:
patent: 4454600 (1984-06-01), LeGresley
patent: 4937828 (1990-06-01), Shih et al.
patent: 5132975 (1992-07-01), Avaneas
patent: 5282214 (1994-01-01), Dravida
patent: 5375127 (1994-12-01), Leak et al.
patent: 5383204 (1995-01-01), Gibbs et al.
patent: 5537403 (1996-07-01), Cloonan et al.
patent: 5568477 (1996-10-01), Galand et al.
patent: 5671238 (1997-09-01), Chen et al.
patent: 5740075 (1998-04-01), Bigham et al.
patent: 5748652 (1998-05-01), Kim
patent: 5787094 (1998-07-01), Cecchi et al.
patent: 5878057 (1999-03-01), Maa
patent: 5953344 (1999-09-01), Dail et al.
patent: 6052815 (2000-04-01), Zook
patent: 6122759 (2000-09-01), Ayanoglu et al.
patent: 6134597 (2000-10-01), Rieth et al.
patent: 6167389 (2000-12-01), Davis et al.
patent: 6188699 (2001-02-01), Lang et al.
patent: 6223320 (2001-04-01), Dubey et al.
patent: 6357032 (2002-03-01), Plotz et al.
patent: 6560746 (2003-05-01), Morsberger
Albertengo et al., Parallel CRC Generation, Oct. 1990 IEEE, pp. 63-71.
Pei et al., High-Speed Parallel CRC Circuits in VLSI, vol. 40, No. 4, Apr. 1992 IEEE, pp. 653-656.
McClannahan et al., High-Speed Parallel Cyclic Redundancy Check Generator, vol. 33, No. 5, Oct. 1990 IBM Technical Disclosure Bulletin.
Connolly Brian J.
Leonard Todd E.
Lin Ming-I M.
Mann Gregory J.
Raymond Jonathan H.
Chaudry Mujtaba K.
De'cady Albert
International Business Machines - Corporation
Schmeiser Olsen & Watts
Steinberg William H.
LandOfFree
Multilevel parallel CRC generation and checking circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilevel parallel CRC generation and checking circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel parallel CRC generation and checking circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3778979