Multilevel metallization process for integrated circuits

Details Multilevel metallization process for integrated circuits Multilevel metallization process for integrated circuits

1980-10-28

1984-03-13

Hess, Bruce H.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29590, 29591, 156657, 357 71, C23F 102

Patent

active

044365829

ABSTRACT:
A multilevel metallization process which allows fabrication of several types of high density MOS and bipolar integrated circuits. The process uses a pad located under the inter-layer contact opening. The material of the pad is poly-silicon (doped or undoped), a refractory metal, or a refractory metal silicide which is not capable of being attacked during chemical etching of the metallization layers. If poly-silicon is used, it is either doped during its deposition or during contact doping, or it is automatically silicided during ohmic and Schottky contact formations.

REFERENCES:
patent: 4078963 (1978-03-01), Symersky

Affiliated with

Also associated with

Rating

Multilevel metallization process for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel metallization process for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel metallization process for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-490919