Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-03-04
2000-05-23
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438660, 438656, 438674, 438688, H01L 214763
Patent
active
060665580
ABSTRACT:
The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film. The metal layer is made to flow into the hole by reflowing, to completely fill the hole and to planarize the surface of the metal layer. The metal layer is subjected to be patterned, to form a wiring layer of a second layer, after the surface of the metal layer is planarized by the reflowing.
REFERENCES:
patent: 5169803 (1992-12-01), Miyakawa
patent: 5637534 (1997-06-01), Takeyasu et al.
patent: 5789317 (1998-08-01), Batra et al.
Hosaka Shigetoshi
Kawano Yumiko
Kobayashi Hiroshi
Wada Yuichi
Yano Tetsuya
Everhart Caridad
Tokyo Electron Limited
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