Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-08-05
1999-03-30
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438723, 438700, 438713, 438640, H01L 21469
Patent
active
058889019
ABSTRACT:
A structure and a method for connecting multiple interconnect layers on an integrated circuit structure (10) using landed or non-landed vias. An integrated circuit structure (10) has an interconnect trace (11) formed over a surface. A dielectric layer (13) is formed over the integrated circuit structure (10) and a photoresist layer (14) having an opening in the area where a via is desired is formed on the dielectric layer (13). The dielectric layer (13) is isotropically etched in an upper portion (16) through the opening in the photoresist layer (14) and then anisotropically etched to expose the interconnect trace (11). The photoresist layer (14) is removed and the dielectric layer (13) subjected to a high pressure sputter etch for smoothing the surfaces of the via opening and for filling voids (18) in the dielectric layer (13).
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Everhart Caridad
Hightower Robert F.
Hoshizaki Gary
Motorola Inc.
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