Multilevel interconnection and method for making

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438723, 438700, 438713, 438640, H01L 21469

Patent

active

058889019

ABSTRACT:
A structure and a method for connecting multiple interconnect layers on an integrated circuit structure (10) using landed or non-landed vias. An integrated circuit structure (10) has an interconnect trace (11) formed over a surface. A dielectric layer (13) is formed over the integrated circuit structure (10) and a photoresist layer (14) having an opening in the area where a via is desired is formed on the dielectric layer (13). The dielectric layer (13) is isotropically etched in an upper portion (16) through the opening in the photoresist layer (14) and then anisotropically etched to expose the interconnect trace (11). The photoresist layer (14) is removed and the dielectric layer (13) subjected to a high pressure sputter etch for smoothing the surfaces of the via opening and for filling voids (18) in the dielectric layer (13).

REFERENCES:
patent: 4641420 (1987-02-01), Lee
patent: 4690746 (1987-09-01), McInerney et al.
patent: 5089442 (1992-02-01), Olmer
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5269880 (1993-12-01), Jolly et al.
patent: 5453403 (1995-09-01), Meng et al.
patent: 5460689 (1995-10-01), Raaijmakesr et al.
patent: 5560802 (1996-10-01), Chisholm
patent: 5707486 (1998-01-01), Collins
R. Iyer, "Reactive Facet Sputtering of SiO.sub.2 ", J. Electrochem. Soc., vol. 141, No. 11, Nov. 1994, pp. 3151-3153.
Chisato Hashimoto et al., "New taper-etching technology using oxygen ion plasma", J. Vac. Sci. Technol., vol. 8, No. 3, May/Jun. 1990, pp. 529-532.
H. Kotani et al., "Sputter-Etching Planarization for Multilevel Metallization", J. Electrochem Soc.: Solid-State Science and Technology, vol. 130, No. 3, Mar. 1983, pp. 645-648.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multilevel interconnection and method for making does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel interconnection and method for making, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel interconnection and method for making will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1214570

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.