Multilevel interconnect structure with low-k dielectric

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S763000, C257S522000

Reexamination Certificate

active

07138718

ABSTRACT:
A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

REFERENCES:
patent: 4918032 (1990-04-01), Jain et al.
patent: 4933743 (1990-06-01), Thomas et al.
patent: 5018256 (1991-05-01), Hornbeck
patent: 5148260 (1992-09-01), Inoue et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5565706 (1996-10-01), Miura et al.
patent: 5708303 (1998-01-01), Jeng
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5757079 (1998-05-01), McAllister et al.
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5798559 (1998-08-01), Bothra et al.
patent: 5872402 (1999-02-01), Hasegawa
patent: 5950102 (1999-09-01), Lee
patent: 6040628 (2000-03-01), Chiang et al.
patent: 6060383 (2000-05-01), Nogami et al.
patent: 6060784 (2000-05-01), Oda
patent: 6078088 (2000-06-01), Buynoski
patent: 6090701 (2000-07-01), Hasunuma et al.
patent: 6208029 (2001-03-01), Allman et al.
patent: 6277726 (2001-08-01), Kitch et al.
patent: 6300681 (2001-10-01), Yoh
patent: 6427324 (2002-08-01), Franklin et al.
Togo et al.; “A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs”; 1996 Symposium on VLSI Technology Digest of Technical Papers; pp. 38 and 39.
Anand et al.; “NURA: A Feasible, Gas-Dielectric Interconnect Process”; 1996 Symposium on VLSI Technology Digest of Technical Papers; pp. 82 and 83.
Bohr; “Interconnect Scaling—The Real Limiter to High Performance ULSI”; IEDM 95, pp. 241-244.
Maliniak; “DAC attacks designer issues”; Electronic Design, vol. 43, No. 12, ISSN: 0013-4872, Jun. 12, 1995; 17 pages.
Hong et al.; “The effect of sol viscosity on the sol-gel derived low density SiO2xerogel film for intermetal dielectric application”; Thin Solid Films 332 (1998); pp. 449-454.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multilevel interconnect structure with low-k dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel interconnect structure with low-k dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel interconnect structure with low-k dielectric will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3697868

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.