Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-04-28
1999-12-07
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, H01L 21283
Patent
active
059982934
ABSTRACT:
An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.
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Bandyopadhyay Basab
Brennan William S.
Dawson Robert
Fulford Jr. H. Jim
Hause Fred N.
Advanced Micro Devcies, Inc.
Bowers Charles
Daffer Kevin L.
Whipple Matthaw
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