Multilevel interconnect structure

Details Multilevel interconnect structure Multilevel interconnect structure

1994-02-18

1997-05-06

Thomas, Laura

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174264, 174262, 174257, H05K 109, H05K 114

Patent

active

056273452

ABSTRACT:
A multilevel interconnect structure for use in a semiconductor device includes a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. An interlayer insulating film is deposited on the lower metal wiring and a via hole is formed in the interlayer insulating film. A plug made of aluminum or aluminum alloy is formed in the via hole. An upper metal wiring has an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. The plug directly contacts the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability.

REFERENCES:
patent: 3335489 (1967-08-01), Grant
patent: 4121241 (1978-10-01), Drake et al.
patent: 4172004 (1979-10-01), Alcorn et al.
patent: 4410622 (1983-10-01), Dalal et al.
patent: 4566897 (1986-01-01), Yorikane et al.
patent: 4614021 (1986-09-01), Hulseweh
patent: 4721689 (1988-01-01), Chaloux, Jr. et al.
patent: 4824802 (1989-04-01), Brown et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 4956313 (1990-09-01), Cote et al.
patent: 5151305 (1992-09-01), Matsumoto et al.
patent: 5154949 (1992-10-01), Shindo et al.
patent: 5155576 (1992-10-01), Mizushima
patent: 5179042 (1993-01-01), Mikoshiba et al.
patent: 5209816 (1993-05-01), Yu et al.
patent: 5219639 (1993-06-01), Sugawara et al.
patent: 5229257 (1993-07-01), Cronin et al.
patent: 5229549 (1993-07-01), Yamakawa et al.
patent: 5414222 (1995-05-01), Sen et al.
patent: 5418187 (1995-05-01), Miyanaga et al.
patent: 5429995 (1995-07-01), Nishiyama et al.
patent: 5436412 (1995-07-01), Ahmad et al.
patent: 5440075 (1995-08-01), Kawakita et al.
patent: 5478972 (1995-12-01), Mizutani et al.
patent: 5486492 (1996-01-01), Yamamoto et al.
"A Highly Reliable Sub-Half-Micron Via and Interconnect Technology Using Al Alloy High-Temperature Sputter Filling", Hiroshi Nishimura et al., 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 74-75, 1992 IEEE.
"Reliable Submicron Vias Using Aluminum Alloy High Temperature Sputter Filling" Hiroshi Nishimura et al., Jun. 11-12, 1991 VMIC Conference, pp. 170-176, 1991 IEEE.
Proceedings of ECS Symposia, vol. 89-6 pp. 26-38, 1989 Stress Induced Migration of Aluminum-Silicon Films: Influencing Factors and Countermeasures.
Reprint from Proceedings of the IEDM--Dec. 6-9, 1987, pp. 205-208 Reliable Tungsten Encapsulated Al--Si Interconnects for Submicron Multilevel Interconnect.
VMIC Conference, Jun. 12-13, 1990, pp. 42-48 A High Performance Four Metal Layer Interconnect System for Bipolar and BiCMOS Circuits.
VMIC Conference, Jun. 12-13, 1990, pp. 21-27 An Advanced Four Level Interconnect Enhancement Module for 0.9 Micron CMOS.
VMIC Conference, Jun. 12-13, 1990, pp. 106-111 Electromigration in a Two-Level Al--Cu Interconnection with W Studs.
IEEE Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, pp. 562-567 Electromigration Reliability for a Tungsten-Filled Via Hole Structure.
Abstract of a Paper by J. Onoe and H. Yamamato in Proc. Workshop, 6th Meeting, 1969, pp. 325-32, Ed. by S. Wong & F. Furukawa, Mater. Res. Sec., Pittsburgh, PA 1990.
IEEE Electronic Device Letters, vol. EDL-8 No. 2, Feb. 1987, pp. 76-78, by R. Mukai et al.
Enver et al., 1990 IEEE VLSI Multilevel Interconnection Conference, p. 149 (Jun. 12, 1990); Digital Equipment Corporation.
Katto et al., ECS Symposia, vol. 89-6 p. 26 (Oct. 9, 1988); Hitachi.
Kwok et al. 1990 IEEE VSLI Multilevel Interconnection Conference, p. 106 (Jun. 12, 1990); IBM.
Yamamoto et al. 1987 International Electron Device Meeting, p. 205 (Dec. 6, 1987); Matsushita.
Wilson et al., 1990 Symposium on VLSI Technology, p. 3 (Jun. 4, 1990); NEC.
Mtsuoka et al., IEEE Transaction on Electron Devices, vol. 37(3), p. 562, 1990 (Mar. 90); Toshiba.
Bollinger et al., 1990 IEEE VLSI Multilevel Interconnection Conference, p. 21 (Jun. 12, 1990); AT & T.
Homma et al., 1990 Symposium on VLSI Technology, p. 3 (Jun. 4, 1990); NEC.
Joshi et al., 1993 International Conference on Solid Waster Devices and Materials, p. 164 (Aug. 29, 1993); IBM.
Nishimura et al., 1993 International Electron Device Meeting, p. 281 (Dec. 5, 1993); Matsushita.
Amazawa et al., 1991 International Electron Device Meeting, p. 265 (Dec. 9, 1991); NTT.
Chen et al., 1990 International Electron Device Meeting, pp. 90-51 to 90-54 .

Affiliated with

Also associated with

Rating

Multilevel interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilevel interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilevel interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2134212