Multilevel IC floorplanner

Details Multilevel IC floorplanner Multilevel IC floorplanner

2006-10-18

2009-10-13

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07603640

ABSTRACT:
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

REFERENCES:
patent: 2006/0190889 (2006-08-01), Cong et al.
patent: 2007/0245281 (2007-10-01), Riepe et al.
Nakatake et al.,“Module Packing Based on the BSG-Structure and IC Layout Applications”, Jun. 1998, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 6, pp. 519-530.
Chang et al., “B*-Trees: A New Representation for Non-Slicing Floorplans”, 2000, Proceedings—Design Automation Conference, pp. 458-463.
Adya et al., “Fixed-outline Floorplanning Through Better Local Search”, 2001, Proceedings—International Conference on Computer Design, pp. 328-334.
Ranjan et al., “Fast Floorplanning for Effective Prediction and Construction”, 2001, IEEE Transactions on VLSI Systems, pp. 341-351.
Chang et al., “Multi-level Placement for Large-Scale Mixed-Size IC Designs”, 2003, Proceddings—Asia South Pacific Design Automation Conference, pp. 325-330.
Khatkhate et al., “Recursive Bisection Based Mixed Block Placement”, 2004, Proceddings—International Symposium on Phys. Design, 6 pages.
Cong et al., “Robust Mixed-Size Placement Under Tight White-Space Constraints”, Nov. 2005, Proceedings—IEEE/ACM International Conference on Computer Aided Design, 8 pages.

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