Multilevel erase pulse for amorphous memory devices

Details Multilevel erase pulse for amorphous memory devices Multilevel erase pulse for amorphous memory devices

1979-01-24

1980-09-30

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Amorphous

357 2, G11C 700

Patent

active

042259460

ABSTRACT:
The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.

REFERENCES:
patent: 3827033 (1974-07-01), Quilliam
patent: 3846767 (1974-11-01), Cohen
patent: 3875566 (1975-04-01), Helbers
patent: 3886577 (1975-05-01), Buckley
patent: 3922648 (1975-11-01), Buckley
Manhart et al., Automatic `Try and Verify` Circuit to Investigate the Reliability of Memory Switching in Amorphous Materials, Journal of Physics E.: Scientific Instruments, 1975, vol. 8, pp. 317-321.

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