Multilevel DRAM sense amplifier

Details Multilevel DRAM sense amplifier Multilevel DRAM sense amplifier

2000-06-05

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S196000

Reexamination Certificate

active

06373766

ABSTRACT:

This invention relates to dynamic random access memories (DRAMs) and more specifically to multilevel DRAMs which store more than one bit per cell, and to a method for sensing and restoring data in such memories.
BACKGROUND OF THE INVENTION
The density of DRAM may be improved by storing more than one bit in an individual memory cell. It may be seen that in this type of memory a single memory cell does not simply store a two valued binary data (one bit), but rather stores four values (for 2 bits/cell), or eight values (for 3 bits/cell) or in the case of an n-valued memory, 1
cells hold the same amount of data as in a conventional binary data system.
An example of this kind of multivalued data memory is described in U.S. Pat. No. 4,841,483, in which one of n-different data values can be stored in each memory cell as one of n-different voltage levels. Furthermore, a bitline is divided into (n−1) sub-bitlines and each sub-bitline is connected through a switch element, whereby the (n−1) sub-bitlines are selectively connected or disconnected. Then when the data is to be read out, with the (n−1) sub-bitlines in the connected state, the memory potential of one memory cell is read out after the switch elements are set to the non-conducting state and the bitline is separated into (n−1) sub-bitlines. Next the voltage on each of the (n−1sub-bitlines is detected using (n−1) sense amplifiers having different standard voltages. On the other hand when data is to be written, with the (n−1) sub-bitlines in the separate state, each sub-bitline is supplied with a voltage corresponding to the data to be written and then the switch elements are put into the conducting state and the (n−1) sub-bitlines are connected together. Thereafter, the bitline potential is determined by capacitive division of the potential of each of the (n−1) sub-bitlines and this potential as written to the selected memory cell.
Other approaches to multilevel memories and sensing and restoring data as described in the following references. U.S. Pat. No. 4,771,404 “Memory Device Employing Multilevel Storage Circuits,” Mano et. al; U.S. Pat. Nos. 5,283,761, 5,532,955, 5,612,912, “Method for Multilevel Sense and Restore,” Gillingham; Aoki et. al, “A 16-level/cell Dynamic Memory,” ISSCC, February 1985; Furuyama, et. al, “An Experimental 2-bit/cell Storage DRAM for Macro Cell or Memory-on Logic Application,” IEEE JSSC April 1989; Ohta, et. al, “A Novel Memory Cell Architecture for High-Density DRAMs,” Symposium on VLSI Circuits, May 1989; Gillingham, “A Sense and Restore Technique for Multilevel DRAM,” IEEE JSSC July, 1996; and Murotani et. al, “A 4-Level Storage 4 Gb DRAM,” ISSCC, February 1997.
The Gillingham, U.S. Pat. Nos. 5,532,955 and 5,612,912 discuss a multilevel DRAM memory architecture that uses a 2-bit per cell storage system, one bit denoted as the sign and the other bit denoted as the magnitude. The memory utilizes a standard folded bitline DRAM architecture with the addition of several switches and a second sense amplifiers in each column. Typically, folded bitlines are divided into two equal sub-bitlines connected by pass transistors, each connected to separate sense amplifiers. The pair of sub-bitlines on the left and on the right of the pass transistors is each connected to separate sense amplifiers. Sensing of the 2-bits is performed sequentially, first the sign bit then the magnitude bit. The sign bit is used to create the reference level for the magnitude of the sense operation. The sensing method involves sharing the stored charge onto both sub-bitlines, which are then isolated, and one of the voltages is then sensed to provide the sign bit. The charge is, in turn, restored into the cell to preserve it while the sub-bitlines are precharged. A reference voltage is then generated by charge sharing the cell which now holds the sign bit between the precharged sub-bitlines. The magnitude bit is then sensed with respect to the generated reference voltage. The restore operation uses a similar concept in reverse order by charge sharing the sign bit charge on two bitlines with the magnitude bit on one bitline.
This above approach involves complex control logic, which must be carefully timed to allow the described charge sharing to occur. Furthermore, a selected word line must be activated twice within one active cycle and must therefore be controlled by two separate row activation paths. Thus the above as well as previous approaches to sensing and restoring data in multilevel DRAMs have been complex and relatively slow. Furthermore, such approaches required precise timing of various control signals to perform both the sense and restore operations.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, there is provided a dynamic random access memory (DRAM) for storing a plurality voltage levels in each of a plurality of memory cells. The memory has a plurality of complementary bit lines each having memory cell capacitors coupled thereto. The bit lines are coupled through memory access transistors for reading data from the memory cells. The bit lines are divided into sub-bit lines by switches. The memory comprises a first and a second group of sense amplifiers. The first group of sense amplifiers is associated with the plurality of bit lines for sensing sign data from selected ones of the plurality of memory cells. The second group of sense amplifiers is associated with the plurality of bit lines for sensing magnitude data from selected ones of the plurality of memory cells. This is done in response to sign data feedback signals from the first group of sense amplifiers, The second group of sense amplifiers includes a plurality of skewed inverters for switching at multiple voltage levels in response to the magnitude data and the feedback sign data.


REFERENCES:
patent: 5699289 (1997-12-01), Takenaka
patent: 5818784 (1998-10-01), Muranaka et al.
patent: 5973957 (1999-10-01), Tedrow

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