Multilevel copper interconnect with double passivation

Details Multilevel copper interconnect with double passivation Multilevel copper interconnect with double passivation

2000-05-31

2004-01-06

Trinh, Michael (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S754000, C257S758000, C257S760000

Reexamination Certificate

active

06674167

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to integrated circuits and in particular to multilayer metal wiring interconnects in an integrated circuit assembly.
BACKGROUND OF THE INVENTION
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together with aluminum wires to define a specific electric circuit, such as a computer memory. The aluminum wires are typically about one micron thick, or about 100 times thinner than a human hair.
To form the aluminum wires, fabricators sometimes use a dual-damascene metallization technique, which takes its name from the ancient Damascene metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components on a wafer with an insulative layer of silicon dioxide, etching small holes in the insulative layer to expose portions of the components underneath, and subsequently etching shallow trenches from hole to hole to define a wiring pattern.
Etching the trenches and holes entails forming a mask, using photolithographic techniques, on the insulative layer. The masks, which typically consists of a material called photoresist, shields some portions of the insulative layer from the etchant and allows the etchant to dissolve away other portions. After etching, fabricators remove the mask to expose the patterned insulative layer. They then blanket the entire insulative layer with a thin sheet of aluminum and polish off the excess, leaving behind aluminum vias, or contact plugs, in the holes and thin aluminum wires in the trenches.
The complexity of some integrated circuits demand several interconnected levels of wiring. Some circuits, such as microprocessors, have five or six interconnected levels, with each level formed by repeating the basic dual-damascene produce. For example, to form a second wiring level, fabricators apply a new insulative layer over the first wiring layer, form another mask on the new layer, etch holes and trenches into the new layer, remove the mask, blanket the new layer with aluminum, before finally polishing off the excess to complete it.
In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. Fabrication of copper-wired integrated circuits sometimes follows an extension of the dual-damascene method which includes an additional step of lining the holes and trenches of an insulative layer with a copper-diffusion barrier before blanketing the layer with copper and polishing off the excess. (The diffusion barrier is generally necessary because copper atoms readily diffuse through common insulators, such as silicon dioxide, resulting in unreliable or inoperative integrated circuits.) Typically, the copper-diffusion barrier is more than 30 nanometers thick and consists of tantalum, tantalum nitride, tantalum-silicon-nitride, titanium nitride, or tungsten nitride. Filling the barrier-lined holes and trenches with copper generally entails depositing a thin copper seed layer on the copper-diffusion barrier, electroplating copper on the seed layer, and then polishing off the excess.
The present inventors identified at least two problems with using the extended dual-damascene technique for making the copper wiring. The first is that typical copper-diffusion barriers add appreciable resistance to the copper wiring, and thus negate some promised performance advantages. And, the second is that the number of separate procedures or steps necessary to make the copper wiring using the extended technique makes fabrication both costly and time consuming.
In a copending application by K. Y. Ahn and L. Forbes, entitled “Methods for Making Integrated-Circuit Wiring from Copper, Silver, Gold, and other Metals,” application Ser. No. 09/484,303, an electroplated copper technology was disclosed. After fabrication of multilevel copper structure using sacrificial layers of photoresist, a very thin WSiN diffusion barrier was deposited on the copper air-bridge structure by deposition of WSi by CVD, followed by ECR plasma nitridation. The space between the metal lines was then filled with a dielectric material of choice in one step. The WSiN layer thus formed serves to prevent the diffusion of copper into the dielectric material. Furthermore, any unreacted silicon can be converted to a very thin film of SiO
2
or Si
3
N
4
in order to provide a substantial amount of protection against electrochemical corrosion due to moisture and impurities in the dielectric layer.
The passivation bestowed by the extremely thin silicide/oxide or silicide
itride layers formed above may prove to be quite sufficient for protecting the metal line air-bridge structures. On the other hand, the metal line air-bridge
101
is a three-dimensional structure having a large surface area in the aggregate with very small spacings between its numerous top, bottom and side surfaces. Hence, it is possible that the silicide/(SiO
2
or Si
3
N
4
) barriers may contain a very small number of localized structural and chemical defects which could serve as corrosion nucleation centers.
Thus, even with the above described approaches, there is a need for yet improved structures and methods for multilevel Copper interconnects for ULSI circuits.
SUMMARY OF THE INVENTION
The above mentioned problems associated with integrated circuit size and performance, the via and metal line formation process, and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The structures and methods of the present invention include a method for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the number of multilayer metal lines. The silicide layer is oxidized. And, a low dielectric constant insulator is deposited to fill a number of interstices created by the number of air gaps between the number of multilayer metal lines. In one embodiment, forming the number of multilayer metal lines includes a first conductor bridge level. In one embodiment, forming a silicide layer on the number of multilayer metal lines includes using pyrolysis of silane in the presence of a dopant source at a temperature of approximately 325 degrees Celsius. Also, in one embodiment, a metal layer is formed on the oxided silicide layer. The metal layer includes a metal layer selected from the group consisting of Aluminum, Chromium, Titanium, and Zirconium. In one embodiment, the metal layer includes a layer of Aluminum oxide.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4762728 (1988-08-01), Keyser et al.
patent: 5413962 (1995-05-01), Lur et al.
patent: 5891797 (1999-04-01), Farrar
patent: 5-267643 (1993-10-01), None
Bae, S., et al., “Low-Temperature Deposition Pathways to Silicon Nitride, Amorphous Silicon, Polycrystalline Silicon, and n type Amorphous Silicon Films Using a High Density Plasma System”,IEEE Conference Record—Abstracts, International Conference

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