Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-31
2003-07-08
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S124000, C711S144000, C711S146000, C711S156000
Reexamination Certificate
active
06591341
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention provide a multilevel cache system and method. In particular, the present invention relates to a cache system that has multiple cache hierarchies.
BACKGROUND
Many computer, systems use multiple levels of caches to cache data from a memory device. For example, a computer system may have a level one cache (L
1
) and a larger level two cache (L
2
), in addition to an even larger RAM memory. The L
1
cache typically contains a copy of information that was previously loaded from RAM by the processor, and the L
2
cache typically contains both a copy of information in the L
1
cache and other information that had been loaded from RAM by the processor less recently than the information in the L
1
cache.
Each of the caches in such computer systems contain a data array, which stores information copied from the memory, and a tag array, which stores a directory of the information that is contained in the corresponding data array. Using the example above, the system would have an L
1
data array, an L
1
tag array that contains a directory of information in the L
1
data array, an L
2
data array, and an L
2
tag array that contains a directory of information in the L
2
data array. In addition, many computer systems also have multiple translation lookaside buffers (TLB). The TLBs may be used to implement the virtual address system (e.g., to translate from virtual addresses to physical addresses) and to prevent programs from accessing protected areas of memory.
When the processor in the example system described above issues a memory load request, this request is broadcast to the L
1
cache system, including the L
1
TLB, L
1
tag array, and L
1
data array. The L
1
tag array is examined to determine if the requested information is in the L
1
data array. If the requested information is in the L
1
data array, the information is returned from the L
1
data array to the processor. If a search of the L
1
tag array indicates that the information is not in the L
1
cache, then a cache miss is forwarded to the L
2
cache. This causes a request to be sent to the L
2
tag array and L
2
data array. If a search of the L
2
tag array indicates that the requested information is in the L
2
data array, the information is returned from the L
2
data array to the processor. If such a search indicates that the requested information is not in the L
2
data array, then the request is forwarded to the next level in the memory hierarchy, which may be another cache or may be the system RAM.
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Lee et al., “Shared tag for MMU and cache memory,” pp 77-80, CAS '97 Proceedings, vol. 1, IEEE, Oct. 1997.*
Lee et al., “Indirectly-compared cache tag memoryusing a shared tag in a TLB,” pp 1764-1766, Electronics Letters, vol. 3, No. 21, Oct. 1997.
Ellis Kevin L.
Elmore Stephen
Intel Corporation
Kenyon & Kenyon
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