Multilayered through via

Details Multilayered through via Multilayered through via

2011-06-21

2011-06-21

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21597, C257SE23011, C257SE23067, C257SE23174, C257S698000, C257S621000, C257S763000

Reexamination Certificate

active

07964502

ABSTRACT:
A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

REFERENCES:
patent: 5407698 (1995-04-01), Emesh
patent: 6255204 (2001-07-01), Tobin et al.
patent: 6271129 (2001-08-01), Ghanayem et al.
patent: 6271592 (2001-08-01), Kim et al.
patent: 6475907 (2002-11-01), Taguwa
patent: 6503840 (2003-01-01), Catabay et al.
patent: 6569759 (2003-05-01), Taguwa
patent: 6593233 (2003-07-01), Miyazaki et al.
patent: 6670267 (2003-12-01), Fortin
patent: 6674171 (2004-01-01), Yamaguchi
patent: 6787913 (2004-09-01), Yamada et al.
patent: 7399706 (2008-07-01), Omoto et al.
patent: 7517798 (2009-04-01), Tuttle
patent: 7633165 (2009-12-01), Hsu et al.
patent: 7683458 (2010-03-01), Akram et al.
patent: 7777323 (2010-08-01), Kwon et al.
patent: 2009/0160061 (2009-06-01), Hsu et al.
patent: 2009/0176362 (2009-07-01), Akram et al.
patent: 2009/0243046 (2009-10-01), Shi et al.
patent: 2010/0035430 (2010-02-01), Andry et al.
patent: 2010/0237502 (2010-09-01), Yu et al.
patent: 2337151 (1999-11-01), None
patent: 06-151815 (1994-05-01), None
Clark et al; “Integrated Deposition and Etchback of Tungsten in a Multi-Chamber, Single-Wafer System”; June 1990 VMIC Conference, IEEE, pp. 478-485.
Kikuchi et al; “Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs”; Japanese Journal of Applied Physics, vol. 47, No. 4, 2008, pp. 2801-2806.

Affiliated with

Also associated with

Rating

Multilayered through via does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilayered through via, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayered through via will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2683725