Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-10
2002-06-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000, C257S309000
Reexamination Certificate
active
06410954
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to capacitor structures for metal-oxide-semiconductors (MOS), and in particular, to a capacitor structure for deep sub-micron complementary metal-oxide semiconductors (CMOS), formed by multiple levels of electrically conductive concentric lines.
BACKGROUND OF THE INVENTION
Conventional capacitor structures for deep sub-micron CMOS are typically constructed with two flat parallel plates separated by a thin dielectric layer. The plates are formed by layers of conductive material, such as metal or polysilicon. The capacitor structure is usually isolated from the substrate by an underlying dielectric layer. To achieve high capacitance density in these structures, additional plates are provided.
FIG. 1
illustrates a conventional multilayer parallel plate capacitor structure
10
in a deep sub-micron CMOS. The capacitor structure
10
includes a vertical stack of electrically conductive lines
12
separated by dielectric layers
13
. The conductive lines
12
and dielectric layers
13
are constructed over a semiconductor substrate
11
. The conductive lines
12
form the plates or electrodes of the capacitor
10
. The plates
12
are electrically connected together in an alternating manner such that all the “A” plates are of a first polarity and all the “B” plates are of a second polarity, opposite to the first polarity.
A major limitation associated with parallel plate capacitor structures is that the minimum distance between the plates does not change as geometries in CMOS processes are scaled down. Hence, gains in capacitance density are not realized during such down scaling.
Various other capacitor structures with high capacitance densities, such as double polysilicon capacitors and gate-oxide capacitors, are known in the art. Double polysilicon capacitors, however, do not lend themselves to deep sub-micron CMOS processes. Gate-oxide capacitors are generally not used in deep sub-micron CMOS processes because they have large gate areas which cause yield and reliability issues, they generate capacitances which vary with voltage, and may experience high voltages that can breakdown the gate-oxide.
Trench capacitor structures for dynamic random access memories (DRAMs) have high capacitance densities. Such capacitors are formed by etching a trench in the substrate and filling the trench with conductive and dielectric material to form a vertical capacitance structure. However, trench capacitors are costly to fabricated because they add etching and trench filling processes.
Interdigitated capacitor structures are used in microwave applications. These capacitors have closely placed, interdigitated conductive line structures which produce fringing and crossover capacitances therebetween to achieve capacitance. However, the cross-over capacitance produced by interdigitated capacitors is limited to a single conductor level.
Accordingly, a need exists for an improved high capacitance density capacitor structure for deep sub-micron CMOS.
SUMMARY OF THE INVENTION
A capacitor structure comprising a first and at least a second level of electrically conductive concentric lines. The conductive lines of the at least second level overlie the conductive lines of the first level. A dielectric material is disposed between the first and second levels of conductive lines and between the conductive lines in each of the first and second levels. The conductive lines are electrically connected in an alternating manner to terminals of opposing polarity so that capacitance is generated between adjacent lines in each level and in adjacent levels. The capacitor especially useful in deep sub-micron CMOS.
REFERENCES:
patent: 4427457 (1984-01-01), Carlson et al.
patent: 5241201 (1993-08-01), Matsuo et al.
patent: 5583359 (1996-12-01), Ng et al.
patent: 5633532 (1997-05-01), Sohara et al.
patent: 5558561 (1980-05-01), None
patent: 4-318963 (1992-11-01), None
Sowlati Tirdad
Vathulya Vickram
Koninklijke Philips Electronics , N.V.
Thomas Tom
Vu Hung Kim
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