Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2011-01-11
2011-01-11
Davis, Daborah Chacko (Department: 1722)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S678000, C257SE21499, C257SE21505, C438S108000, C430S311000
Reexamination Certificate
active
07868464
ABSTRACT:
A multilayer substrate according to the present invention includes a plurality of laminated insulating layers and conductive patterns formed between the respective insulating layers. The conductive patterns include a first conductive pattern having a predetermined thickness and a second conductive pattern thicker than the first conductive pattern. The first and second conductive patterns are located in the same layer. The first conductive pattern is formed by pattern-etching a conductive layer having a uniform thickness by the subtractive method. The second conductive pattern is formed by forming a pattern-forming groove and then filling the inside of the pattern-forming groove with a conductive material simultaneously with forming a via hole. The first conductive pattern is suitable for an LC pattern for a high-frequency circuit requiring small variations in the width and the thickness of the pattern as well as accuracy in the thickness relative to an insulating pattern, and for a normal conductive pattern requiring impedance matching. The second conductive pattern is suitable for an L pattern for a choke coil.
REFERENCES:
patent: 4926239 (1990-05-01), Fujita et al.
patent: 4941255 (1990-07-01), Bull et al.
patent: 5745984 (1998-05-01), Cole, Jr. et al.
patent: 5994166 (1999-11-01), Akram et al.
patent: 6104093 (2000-08-01), Caletka et al.
patent: 6136668 (2000-10-01), Tamaki et al.
patent: 6175157 (2001-01-01), Morifuji
patent: 6338980 (2002-01-01), Satoh
patent: 6489685 (2002-12-01), Asahi et al.
patent: 6525414 (2003-02-01), Shiraishi et al.
patent: 6555924 (2003-04-01), Chai et al.
patent: 6582991 (2003-06-01), Maeda et al.
patent: 6753483 (2004-06-01), Andoh et al.
patent: 6784530 (2004-08-01), Sugaya et al.
patent: 6930258 (2005-08-01), Kawasaki et al.
patent: 6969554 (2005-11-01), Kashiwagi et al.
patent: 7547975 (2009-06-01), Takaya et al.
patent: 2001/0018242 (2001-08-01), Kramer et al.
patent: 2001/0036711 (2001-11-01), Urushima
patent: 2002/0106893 (2002-08-01), Furukawa et al.
patent: 2003/0001283 (2003-01-01), Kumamoto
patent: 2003/0013233 (2003-01-01), Shibata
patent: 2004/0145858 (2004-07-01), Sakurada
patent: 2004/0178482 (2004-09-01), Bolken et al.
patent: 2005/0142696 (2005-06-01), Tsai
patent: 2006/0021791 (2006-02-01), Sunohara et al.
patent: 2007/0045793 (2007-03-01), Tanaka
patent: 1327710 (2001-12-01), None
patent: 1395461 (2003-02-01), None
patent: 1503338 (2004-06-01), None
patent: 0 370 745 (1990-05-01), None
patent: 1225629 (2002-07-01), None
patent: 1503409 (2005-02-01), None
patent: A-S59-227185 (1984-12-01), None
patent: A-H63-280496 (1988-11-01), None
patent: 2529987 (1989-07-01), None
patent: A-H05-299816 (1993-11-01), None
patent: A-H08-293659 (1996-11-01), None
patent: 09-321408 (1997-12-01), None
patent: 2857279 (1998-11-01), None
patent: A-H10-313152 (1998-11-01), None
patent: 10-322021 (1998-12-01), None
patent: 11-274241 (1999-10-01), None
patent: A-H11-307888 (1999-11-01), None
patent: A-2001-053421 (2001-02-01), None
patent: A-2001-185663 (2001-07-01), None
patent: 2001-250902 (2001-09-01), None
patent: 2001-339165 (2001-12-01), None
patent: 2002-050874 (2002-02-01), None
patent: 2002-170840 (2002-06-01), None
patent: 2002-217656 (2002-08-01), None
patent: 2002-246500 (2002-08-01), None
patent: 2002-246507 (2002-08-01), None
patent: A-2002-217656 (2002-08-01), None
patent: 2002-290051 (2002-12-01), None
patent: 2003-007896 (2003-01-01), None
patent: 2003-37205 (2003-02-01), None
patent: 2003-197655 (2003-07-01), None
patent: A-2003-347748 (2003-12-01), None
patent: 2005-064470 (2005-03-01), None
patent: WO 03/065778 (2003-08-01), None
U.S. Appl. No. 11/527,829, filed Sep. 27, 2006, Kawabata et al.
European Search Report and Opinion dated Nov. 6, 2007 and attachments (9 pages).
Dibble E. P., et al: “Considerations for Flip Chip,” Advance Packaging, IHS Publishing Group, US, vol. 6, No. 3, May 1997, pp. 28-30, XP000694608, ISSN: 1065-0555.
U.S. Appl. No. 10/900,458, filed Jul. 28, 2004, Minoru Takaya et al.
Japanese Office Action received Feb. 13, 2007 and its excerpt translation in English.
European Search Report from the European Patent Office, dated Aug. 9, 2006.
State Intellectual Property Office (SIPO) Office Action dated Mar. 20, 2009 (4 pages).
State Intellectual Property Office (SIPO) Office Action dated Jan. 8, 2010 (4 pages).
English language translation of a State Intellectual Property Office of (SIPO) Office Action dated Apr. 26, 2010 (6 pages).
Abe Hisayuki
Katsumata Masashi
Kawabata Ken-ichi
Chacko Davis Daborah
TDK Corporation
Wolff Kevin Alan
Wolff Law Offices PLLC
LandOfFree
Multilayer substrate and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multilayer substrate and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer substrate and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2725997