Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
2002-10-28
2003-09-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S622000, C257S797000
Reexamination Certificate
active
06617669
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, relates to a semiconductor device that can reduce an area occupied by an alignment mark such as a scribe line formed in an alignment area and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device having a multilayer wiring structure is formed by means of stacking a plurality of insulation layers or wiring layers using a photolithography, but an alignment mark is used in positioning the patterns transferred by the photolithography with respect to each layer. The alignment marks have various shapes according to the exposing system, but, generally, are formed by means of arranging marks having angle of several &mgr;m in several to several tens of matrix shapes. The positioning of a semiconductor substrate is performed by means of exposing the alignment mark to a laser beam and detecting the reflected right thereof. Then, after a layer is formed, wiring and through holes are formed by means of performing process such as etching to the layer using a resist pattern to which a mask pattern is transferred.
In this case, a method of manufacturing a semiconductor device using the conventional alignment mark will be discussed with reference to
FIGS. 1A through 1G
(first prior art).
FIGS. 1A through 1G
are cross sectional views schematically and sequentially showing a forming method of an alignment mark in the manufacturing processes of the semiconductor device according to the first prior art, and illustrate cross sections of an alignment area such as a scribe line. Also, this prior art shows only an alignment area, and does not show a circuit pattern area where transistor and the like are formed.
First, predetermined transistor, etc. are formed (not shown) in a circuit pattern area of a semiconductor substrate such as Si (not shown). Next, as shown in
FIG. 1A
, a first insulation layer
1
comprised of a silicon oxide film, etc. is formed, and then, after a metal layer of Al, etc. is deposited, a resist layer is formed, and then, an alignment is performed by using a mark (not shown) previously formed on the semiconductor substrate which becomes a base as a reference, after that, the resist layer is exposed. And, process such as a dry etching is carried out by using a resist pattern formed by the exposure as a mask, so that a first wiring layer is formed in the circuit pattern area, and at the same time, an alignment mark
2
a
comprised of the same metal layer as the first wiring layer is formed in the alignment area such as the scribe line. Further, the alignment mark explained in the prior art is comprised of about several tens of rows with three columns of marks arranged at predetermined intervals, and the cross section of a line direction will be explained.
Next, after a second insulation layer
3
is deposited on the first wiring layer, a resist layer is formed, and an exposure is carried out by means of using the alignment mark
2
a
as a reference. And, a dry etching process is performed by using a resist pattern formed by the exposure as a mask, so that first through holes are formed in the circuit pattern area, and at the same time, an alignment mark
3
a
in which the first through holes are arranged is formed in the alignment area.
In addition, the first through holes are formed on the first wiring layer in the circuit pattern area which is not shown, but because the first wiring layer is not formed under the second insulation layer
3
in the alignment area shown in
FIG. 1A
, the thickness of the second insulation layer
3
is thicker than that of the circuit pattern area. In this case, since the condition of the dry etching to form the through holes are set according to the thickness of the insulation layer in the circuit pattern area, the first through holes in the alignment area do not penetrate the second insulation layer
3
, and have a shape that the etching is stopped in the middle portion of the second insulation layer
3
.
Next, as shown
FIG. 1B
, after a metal layer such as Al is deposited on the second insulation layer
3
, a predetermined resist layer (not shown) is formed, and then, a resist pattern (not shown) is formed by performing an alignment by using the alignment mark
3
a
depositing the metal layer as a reference. A dry etching process is performed by means of using the resist pattern as a mask, so that a second wiring layer
4
is formed in the circuit pattern area. In addition, as shown in
FIG. 1C
, an alignment mark
4
a
is formed in the alignment area.
Next, as shown in
FIG. 1D
, after a third insulation layer
5
is deposited on the second wiring layer
4
, a predetermined resist layer (not shown) is formed, and then, an exposure is performed by using the alignment mark
4
a
formed of the second wiring layer
4
as a reference, so that a resist pattern (not shown) having a predetermined opening is formed. After that, a dry etching is performed by means of using the resist pattern as a mask, so that second through holes penetrating the third insulation layer
5
are formed in the circuit pattern area, and at the same time, an alignment mark
5
a
in which the second through holes are arranged is formed in the alignment area.
Next, as shown in
FIG. 1E
, after a metal layer such as Al is deposited on the third insulation layer
5
, a predetermined resist layer is formed, and then, an alignment is performed by using the alignment mark
5
a
depositing the metal layer as a reference, so that a resist pattern (not shown) is formed. A dry etching process is performed by using the resist pattern as a mask, so that a third wiring layer
6
is formed in the circuit pattern area, and at the same time, as shown in
FIG. 1F
, an alignment mark
6
a
is formed in the alignment area. After that, a semiconductor device as shown in
FIG. 1G
in which a plurality of wiring layers (seven layers in this prior art) are stacked is manufactured by repeating the same processes sequentially.
As such, conventionally, when forming the patterns of each wiring layer
4
,
6
, an alignment is performed by using the alignment marks
3
a
,
5
a
comprised of the through holes of the insulation layers
3
,
5
just under the wiring layers
4
,
6
, and alignment marks
4
a
,
6
a
comprised of a wiring metal are newly formed on the alignment area such as a scribe line, on the other hand, when forming the through holes in each insulation layer
3
,
5
, an alignment is performed by using the alignment marks
2
a
,
4
a
comprised of the wiring layers
2
,
4
just under the insulation layers, and the alignment marks
3
a
,
5
a
comprised of the through holes are formed on the alignment area.
That is, in case of alternately stacking wiring layers and insulation layers, since new alignment marks are formed according to the formation of the wiring layers and the through holes in the insulation layers, the alignment marks having the same number as the sum of the deposited wiring layers and insulation layers are formed in a new place in the alignment area. In detail, in case where seven wiring layers are formed as shown in the present prior art, total fourteen alignment marks including the insulation layers are formed.
However, in the recent semiconductor devices having a multilayer wiring structure, because the number of alignment marks are increased by making in a multilayer form, and at the same time, more accurate alignment is demanded by minuteness, the arranged number of the marks constituting alignment mark are increased, and an area occupied by one alignment mark becomes great. On the other hand, since a shape of the alignment mark are determined by the used exposing system, the shape thereof cannot be changed freely, and the area occupied by the alignment mark in the alignment area such as a scribe line as a whole semiconductor device becomes great, and thus, there is a problem that other accessory or check pattern for confirming the operation of
McGinn & Gibb PLLC
NEC Electronics Corporation
Nelms David
Nguyen Thinh T.
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