Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1997-04-28
1999-11-02
Nguyen, Vinh P.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324761, G01R 3102
Patent
active
059777834
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a probe structure useful for the measurement of electric characteristics of small test objects, a burn-in test performed under high temperatures and the like. More particularly, the present invention relates to a probe structure having a bump as a contact point with the test objects. Such test objects include, for example, a wafer before dicing and a bare die after dicing, both having a semiconductor element formed thereon, a chip size package including such element and a substrate of almost the same size therewith which have been integrated, one including a pad and a bump electrode of a flat or semi-spherical solder ball or gold formed thereon, and the like.
BACKGROUND ART
Conventionally, IC chips have been tested for various characteristics after packing the IC. For example, in a burn-in test which tests characteristics under high temperatures, an IC package is inserted into an IC socket set on a printed board and tested under a load voltage at a high temperature.
Due to a rapid progress in recent years of the development of large-scale integrated circuits such as chip on board, multi chip module and the like, which are prepared by combining a number of integrated circuits formed on a wafer, burn-in test and the like for various characteristics of each IC are required to be run when the IC is in a bare state before packaging, i.e., at the stage of IC chip (die level) or wafer before dicing.
One method for running a test while a chip is at a die level includes forming a flat or semi-spherical solder bump on a pad of an IC chip having a circuit formed thereon, soldering same to a contact part formed on a printed board, and testing under voltage load at a high temperature.
For testing the electric characteristics of a small test object as mentioned above, a probe card has been developed. This comprises a flexible insulating substrate and a contact part (so-called bump) that comes into contact with the contact part of the test object (Japanese Patent Unexamined Publication No. 182672/1987).
In such a probe card, the bump is required to have a lower contact resistance, and superior corrosion resistance and abrasion resistance. To meet the requirements, the outermost layer of a conventional bump has been prepared from gold or hard gold having an improved abrasion resistance achieved by adding about 0.1% nickel and cobalt to the gold, both having smaller contact resistance and superior corrosion resistance.
When gold or hard gold is used to form the outermost layer of a bump, however, the bump is susceptible to troubles such as defective continuity and varying contact resistance, since it is easily deformed upon contact with the electrode pad of a test object, thus lowering reliability as a probe to be repeatedly used for testing.
When a base metal is used as the base of said outermost layer moreover, the outermost gold layer is crushed to expose the base metal, thereby allowing oxidation and corrosion of the base metal.
When the test object is an IC and subjected to a test having a heat history as in a burn-in test, the material of its electrode pad, which is mainly aluminum, is transferred and attached to the gold on the surface of the bump and diffused to increase the contact resistance.
The base metal contained in the hard gold, such as copper and nickel, diffuses to the surface under a high temperature and is oxidized to result in a problematic high contact resistance.
When a test method includes the use of a flat or semi-spherical solder bump formed on the pad of an IC chip, as mentioned above, the solder of the solder bump is heated after testing to melt same and remove the IC chip. This changes the size, volume and shape of the bump formed on the pad of the IC chip, necessitating re-forming of the solder bump. Moreover, the solder remains at the contact part on the printed board after removing the IC, and the solder should be removed every time a timing is run.
Such problems are not specific to a bare chip wafer alone but found with regard to a chip s
REFERENCES:
patent: 5027062 (1991-06-01), Dugan et al.
patent: 5177439 (1993-01-01), Liu et al.
patent: 5575662 (1996-11-01), Yamamoto et al.
Amino Ichiro
Baba Toshikazu
Hino Atsushi
Takayama Yoshinari
Nguyen Vinh P.
Nitto Denko Corporation
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