Dynamic information storage or retrieval – Binary pulse train information signal – Including sampling or a/d converting
Reexamination Certificate
1999-03-19
2001-10-16
Hindi, Nabil (Department: 2651)
Dynamic information storage or retrieval
Binary pulse train information signal
Including sampling or a/d converting
Reexamination Certificate
active
06304539
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a disk memory device which records and reproduces an optical, a magnetic or an optical-magnetic data by using a disk as a record medium, especially, to a signal processing device used to a data reproduction operation.
Conventionally, a disk memory device which optically, magnetically or optical-magnetically records and reproduces data on a disk (storage medium) has a read-out signal processing circuit to reproduce (decode) data (data recorded on the disk) from the read-out signal (read signal) read from the disk with a read head (including a read/write composite head). In the disk memory device, there are a magnetic disk drive which is called hard disk drive (HDD), an optical disk drive, and a magnetic-optical disk drive, specifically. The read-out signal processing circuit is often constructed specifically by an exclusive IC which integrally includes record and reproduction function as a read/write circuit.
The read-out signal processing circuit roughly comprises an amplifier which amplifies the read-out signal read from the head, a waveform equalization circuit to waveform-equalize the read-out signal waveform, a data detection circuit to perform a data detection processing (identification processing of binarization), and a decoder (decoding circuit) to decode to the record data.
The waveform equalization circuit makes the detection error rate in the data detection processing within the permissive range by correcting the waveform distortion caused by the result of passing the record channel (system which consists of the record medium/the head) when data is recorded on the disk. Conventionally, a linear equalization method of correcting linear distortion of the read-out signal by modeling the record channel to the linear system is adopted. Specifically, an adaptive digital filter to adaptively follow to the characteristic change of the record channel is often adopted.
Recently, the signal processing technology of the PRML (Partial Response Maximum Likelihood) method is being adopted as a data detection circuit. This PRML method is a method to sequentially detect data by using the correlation before and behind the read-out signal waveform, and, specifically, the Viterbi decoder is used.
In recent years, for example, a high record density like several Gbits/in
2
has been achieved in HDD to make the memory capacity of the disk memory device mass. In such a high record density, since it is impossible to set a linear model to the binary data recorded on the disk in a response characteristics of the conventional record channel, it is necessary to consider a nonlinear element. Here, when the ratio of a nonlinear distortion becomes large, the equalization residual error increases in the linear equalization circuit, and securing the detection error rate within the permissive range becomes difficult in the data detection processing.
The waveform equalization circuit, which uses a hierarchical network or multilayer perceptron type neural network scheme (Hereafter, so called as a MLP type) is proposed as a method to equalize a nonlinear distortion of the read-out signal waveform. A nonlinear waveform distortion in the read-out signal is removed by the MLP type equalization circuit, then the data detection processing is executed with the conventional data detection circuit.
Here, the FIR (Finite Impulse Response) type linear equalization circuit used with the conventional read-out signal processing circuit is constructed as shown for example in
FIG. 1
, and has a delay circuit of a plurality of taps, multipliers
21
, and adder circuits
22
having a configuration by which delay elements
20
which have the same delay time as the clock cycle of the channel is connected in series. Each multiplier
21
multiplies an equalization coefficient W
n
(gain) to the delayed signal (signal sample value S
n,k
) from each tap and outputs it. Adder circuits
22
add outputs of each multiplier
21
, and output an output value Y
k
of the linear equalization circuit.
On the other hand, the MLP type waveform equalization circuit is constructed as shown for example in FIG.
2
. Here, a configuration of the hidden node
31
shown in
FIG. 2
is almost similar to the FIR type linear equalization circuit shown in above-mentioned FIG.
1
. That is, a signal is input to the delay circuit of a plurality of taps having delay elements
20
which have the same delay time as the channel clock cycle and are connected in series, and all the results of multiplying the delayed signal from each tap by the weighting coefficient are added. The MLP type waveform equalization circuit differs from the FIR type linear equalization circuit, and an output of a hidden node is a value obtained by evaluating an added result of all inputs by the nonlinear function which is called sigmoid function shown in FIG.
3
.
In addition, in the MLP type waveform equalization circuit, the number of hidden layers constructed with a set of hidden nodes which share the layer on the input side without the connection relationship mutually and the numbers of hidden nodes which construct one layer are determined according to the equalization performance requested to the equalization circuit. It is assumed that a hidden layer is one layer, and the number of hidden nodes is j for the simplification in FIG.
2
. Nodes of hidden layers other than a hidden layer which is the nearest the delay line add all of the result of multiplying the output of each hidden node in one pervious stage by the equalization coefficient, and output the value in which the addition result is evaluated by the sigmoid function shown in FIG.
3
. The output node
30
adds all of the result of multiplying the output of each hidden node in one previous stage by the equalization coefficient, and outputs the addition result (d
k
) as it is.
As mentioned above, with a high recording density in the disk memory device, a nonlinear distortion component which is occupied to the distortion element included in the read-out signal waveform when data is reproduced from the disk, increases up to the extent which cannot be disregarded. Therefore, the necessity of the nonlinear waveform equalization processing to remove a nonlinear distortion component becomes large. Therefore, it becomes general that the MLP type waveform equalization circuit is used with the linear equalization circuit in the read-out signal processing circuit. However, though the delay line on the input side of each hidden node in the lowest rank layer can be shared by each hidden node as shown in
FIG. 2
, the multipliers (
21
) to multiply the number of taps of the input delay lines and the numbers of hidden nodes are needed in the MLP type waveform equalization circuit only for constructing a hidden node in the low rank layer. Therefore, the circuit scale of the MLP type waveform equalization circuit becomes large compared with the conventional linear equalization circuit. Moreover, since the MLP type waveform equalization circuit has at least one hidden layer, the number of stages of multipliers increases and the processing time for referring to the sigmoid function increases.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a high capacity and a high performance disk memory device to become able to lower the data detection error rate by removing the influence of the nonlinear distortion component of the read-out signal by using the MLP type waveform equalization circuit, and lower the increase of the circuit scale and the processing time, in the disk memory device which has the read-out signal processing circuit.
A disk memory device according to present invention comprises: a head which reads a data recorded on a disk and outputs a read-out signal; an A/D converter which converts the read-out signal into a digital signal; and a signal processing circuit of a multilayer perceptron type neural network scheme which recieves the digital signal converted by the A/D converter, wherein the signal processing circuit has an input laye
Hindi Nabil
Kabushiki Kaisha Toshiba
Pillsbury & Winthrop LLP
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