Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2000-02-29
2001-08-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S283000
Reexamination Certificate
active
06277676
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88121712, filed Dec. 10, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating the capacitors and devices of a semiconductor device. More particularly, the present invention relates to a method of fabricating the dual polysilicon layer capacitors and the devices of a dual operation voltage mixed-signal integrated circuit.
2. Description of the Related Art
On the eve of the twenty-first century, semiconductor applications continue to expand. A large quantity of semiconductor devices having a variety of functions is used in computer systems, communication equipment and many consumer electronic products.
To cater to some specific customer applications, application-specific integrated circuits (ASIC) are fabricated. In addition, in order for an electronic product to be light, compact and speedy, system on chip (SOC) design is often adopted in the fabrication of semiconductor devices. In other words, separately manufactured electronic devices are now formed in a single silicon chip. Currently, a type of application-specific circuit known as a mixed-signal integrated circuit has been developed. The mixed-signal circuit is formed by integrating a capacitor and a complementary metal oxide semiconductor (CMOS) device together. At first, all the CMOS devices operate at a single gate voltage. Recent advances in manufacturing technologies have made it possible to include two or more types of CMOS devices, each operating at its own operational voltage. For example, an integrated circuit having CMOS devices capable of working in dual or even triple voltage mode are fabricated on a silicon chip.
FIGS. 1A through 1C
are schematic cross-sectional views showing the steps for producing the gate oxide layers of a conventional integrated circuit that operates in dual voltage mode.
As shown in
FIG. 1A
, gate oxide layers
102
are formed on portions of a substrate
100
. The substrate
100
has a well region
104
and shallow trench isolation structures
106
therein. The gate oxide layer
102
is formed by thermal oxidation. A patterned photoresist layer
108
is formed over the substrate
100
, which comprises substrate regions
100
a
and
100
b
. The photoresist layer
108
covers the substrate region
100
a
for forming the desired high operation voltage devices so that the substrate region
100
b
for forming the desired low operation voltage devices is exposed.
As shown in
FIG. 1B
, the gate oxide layer
102
on substrate regions
100
b
is removed while retaining the gate oxide layer
102
a
on the substrate region
100
a.
As shown in
FIG. 1C
, the patterned photoresist layer
108
is removed and then another thermal oxidation is carried out. Hence, a gate oxide layer
110
is formed on the substrate
100
in the substrate region
100
b
. Meanwhile, moisture and oxygen can still diffuse and react with the existing gate oxide layer
102
a
to form a thicker oxide layer
112
.
Consequently, by controlling the parameters during these two thermal oxidations, gate oxide layers of different thicknesses are formed in various regions. Thus, devices having the desired working voltages are formed in desired locations.
In the conventional method of fabricating the dual thickness gate oxide layer, a portion of the gate oxide layer has to be covered by a photoresist layer. Hence, if the photoresist layer is not thoroughly removed, residual defects may remain above the gate oxide layer to compromise device reliability. In addition, if a capacitor having polysilicon upper and lower electrodes needs to be formed at the same time as the gate terminal, only the polysilicon gate layer can serve as the lower electrode of the capacitor. In other words, to form the capacitor, steps still have to be undertaken to form a dielectric layer above the lower electrode followed by an upper electrode above the dielectric layer. Hence, production time and cost are increased.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating the capacitors and devices of a mixed-signal integrated circuit. A substrate having a plurality of shallow trench isolation structures therein is provided. The substrate can be divided into regions for forming capacitors, first devices and second devices. The capacitor is formed above one of the shallow trench isolation (STI) structures. The first devices and the second devices are formed above the substrate between the STI structures. A first gate dielectric layer is formed over the substrate, and then a first conductive layer is formed over the first gate dielectric layer. The first conductive layer and the first gate dielectric layer above the regions for forming the first devices are removed so that the substrate is exposed. A dielectric layer is formed over the first conductive layer and the exposed substrate. A second conductive layer is formed over the dielectric layer. The second conductive layer and the dielectric layer are patterned to form an upper electrode and a capacitor dielectric layer in the capacitor regions. Meanwhile, the second conductive layer and the dielectric layer above the first conductive layer within the second device regions are removed while retaining the second conductive layer and the dielectric layer over the first device regions. The capacitor region and the first conductive layer and the first gate dielectric layer in the first device region are patterned. Ultimately, a lower electrode is formed in each capacitor region, a second gate dielectric layer and a first gate terminal are formed in each first device region and a third gate dielectric layer and a second gate terminal are formed in each second device region.
According to the invention, the steps of forming the mixed-signal integrated circuit includes sequentially forming a gate dielectric layer and a first conductive layer over the substrate regions for forming the high voltage devices and the capacitors. Thereafter, a dielectric layer and a second conductive layer are sequentially formed over the first conductive layer and the substrate region for forming the low voltage devices. Photolithographic and etching processes are conducted twice to pattern the gate dielectric layer, the first conductive layer, the dielectric layer and the second conductive layer so that the gate terminals of the high and low voltage devices as well as the capacitor are formed at the same time.
Accordingly, the present invention is to provide an improved method of fabricating the capacitors and the devices of a mixed-signal integrated circuit. The method prevents possible formation of residual defects over gate oxide layers that has been covered by photoresist and simplifies the process of fabricating the capacitor by integrating some of the steps for forming the dielectric layer and the polysilicon upper electrode.
In the patterning process, since the photoresist layer is not in direct contact with the gate dielectric layer, reliability of the gate dielectric layer is improved. In addition, the lower electrodes of the capacitors and the gate terminals of the high voltage devices are formed together in the same step. The gate dielectric layer of the low voltage devices and the dielectric layer of the capacitor are formed together in the same step. Similarly, the gate terminal of the low voltage devices and the upper electrodes of the capacitors are formed together in the same step. Hence, the steps involved in the invention can be easily integrated with standard CMOS fabrication procedure for a higher yield.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5889315 (1999-03-01), Farrenkopf et al.
patent: 6022794 (2000-02-01), Hsu
patent: 6030872 (2000-02-01), Lu et al.
patent: 6034416 (2000-03-01), Uehara et al.
Dang Phuc T.
Huang Jiawei
J.C. Patents
Nelms David
Taiwan Semiconductor Manufacturing Co. Ltd.
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